Commit Graph

50283 Commits

Author SHA1 Message Date
Ritul Guru f123ffe78c mb/amd/mayan: Add framework for morgana crb mayan
mayan is the reference board for the morgana SoC. It needs to be
updated to match the actual board design as well. amd/mayan is started
as a copy of amd/birman.

Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70010
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-27 17:18:13 +00:00
Frank Chu 21e0da3128 mb/google/brya/var/marasov: Update gpio table
Based on latest schematic to update the gpio table.

BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I03b443826d39182eaf23ad3e4e0ba8d6b8a93022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69180
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-26 23:55:18 +00:00
Kapil Porwal d6152ea1af mb/google/rex: Disable SATA from the devicetree
SATA is not supported on google/rex hence disable it.

BUG=none
TEST=Build and boot to google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I35a742ab9782feed86c3af514505d870d181b34b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26 23:53:29 +00:00
Saurabh Mishra 060492ecd2 vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.h
Fix compilation issue due to enum macro redefinition by safeguarding
definitions with DISPLAY_FSP_VERSION_INFO_2 in SoC Kconfig.

Back-ported from commit f7e8adac7b ("edk2-stable202005: Update
MdePkg/Include/IndustryStandard/SmBios.h") to fix compilation issue due
to enum macro redefinition.

BUG=b:260183604
TEST=Verify MTL Rex0 build with the patch
and verify the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2022-11-26 23:45:26 +00:00
Elyes Haouas 9018dee685 src/soc/intel: Remove unnecessary space after casts
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26 23:39:16 +00:00
Reka Norman 5aa98964fb mb/google/nissa/var/craask: Add support for NVMe
Enable NVMe GPIOs based on fw_config and add NVMe to devicetree.

Note, eMMC and NVMe are not probed in devicetree. On first boot in
factory, the device needs to boot with unprovisioned fw_config, so all
storage devices should be enabled when unprovisioned. Currently,
devicetree disables all probed devices when unprovisioned. If we want
eMMC and NVMe to be probed, support needs to be added for enabling
probed devices when unprovisioned.

BUG=b:259211172
TEST=Verified by ODM. On craask, LTE and WCAM still work. On craaskneto,
eMMC and NVMe SKUs can both boot.

Change-Id: I76a056cddff2246cfb5bb26ddbdfc333b49d9aaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69958
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-26 23:38:43 +00:00
Subrata Banik fb970a43bd soc/intel/meteorlake: Refactor heci finalize functions
This patch creates a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again FSP config.

Currently, `heci_set_to_d0i3()` function is getting called twice.

BUG=b:260041679
TEST=Able to build google/rex with this patch and observe coreboot log
modification as below:

Without this patch:

[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 29 / 78 ms

With this patch:

[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 28 / 52 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-26 08:42:21 +00:00
Subrata Banik a3c0ba12eb soc/intel/alderlake: Use common code CSE-Lite API for WP information
This patch drops the local implementation
`log_me_ro_write_protection_info` and adopts the API from IA common
code (cse_lite.c).

BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69969
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-26 08:41:56 +00:00
Subrata Banik da527ec12b soc/intel/cmn/cse: Create API to get CSE Lite WP Information
This patch creates an API for CSE-Lite specific SKU to retrieve the
Write Protect (WP) information (`cse_log_ro_write_protection_info`)
like WP range and limit, if the region is write-protected or not etc.

BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-26 08:41:49 +00:00
Felix Singer 11433c8e98 3rdparty/libgfxinit: Update submodule pointer to 066e52eeaa32
Change-Id: I9b36a4b5f0a7a075ddef5d4bec984f3cd131626d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-26 08:11:52 +00:00
Felix Singer e12f3bf6e2 3rdparty/libhwbase: Update submodule pointer to 8be5a82b85ce
Change-Id: I5ad61c39125b19922ae2fdda9767544d857139d0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-26 08:11:42 +00:00
Elyes Haouas b961910192 Update arm-trusted-firmware submodule to upstream v2.8.0
Updating from commit id 61fe7826d:
2022-10-18 16:20:05 +0200 - (Merge "feat(fvp): build delegated attestation in BL31" into integration)

to commit id 9881bb93a:
2022-11-21 19:12:00 +0100 - (Merge "docs(spm): update threat model" into integration)

This brings in 227 new commits.

Change-Id: I6c902a7360b5436df22c829c7e387457598c3b94
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-26 02:11:43 +00:00
Ian Feng c6e6d0d522 mb/google/nissa/var/xivu: Update DPTF parameters
Follow thermal table from thermal team.

1. Modify TS1 passive policy to 68.

BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25 16:41:57 +00:00
Mario Scheithauer 68fb5437f9 mb/siemens/mc_ehl2: Disable L1 prefetcher
As for mainboard mc_ehl1, a hard real-time dependency is also required
for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive
which in the end leads to an increased number of cache misses. Disabling
the L1 prefetcher boosts up the performance (in some cases by more than
10 %) in this specific use case.

Change-Id: I07b27dd672533e693a6c2987d16f54333850760e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-25 15:44:46 +00:00
Arthur Heymans 3627f2903c cpu/intel/model_2065x: Don't use a magic APIC
Move the chip configuration to the cpu cluster device.

It looks like none of the devicetree were featuring a lapic 0xacac,
nor was tcc_offset ever set, so this remains a NOP.

Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-25 15:04:17 +00:00
Kyösti Mälkki a5fa534705 ACPI: Flag boards with ACPI_NO_MADT
These boards do no fill MADT with useful information.

Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25 15:03:47 +00:00
Arthur Heymans dd96ab6987 cpu/intel/haswell: Move chip_ops to cpu cluster
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.

Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-25 15:03:39 +00:00
Kyösti Mälkki c87814d750 ACPI MADT: Add LINT1 as NMI source
Set of boards and platforms did not have LINT1 configured
as NMI source.

Change-Id: I65044125562bda363b3a0d92da6137c77a28b587
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69528
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25 15:02:47 +00:00
Kyösti Mälkki 66b5e1b32d ACPI: Use common code for MADT LAPIC NMIs
Use the broadcast ID to deliver LINT1 as NMI to all CPUs,
instead of listing individual LAPIC IDs.

Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25 15:01:49 +00:00
Kapil Porwal da1a58a503 {drivers/wifi, mb/google}: Rename `is_untrusted` to `add_acpi_dma_property`
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it
makes sense to have a unified name across different device drivers.

BUG=b:259716145
TEST=Verified that the _DSD object is still present in the SSDT.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69937
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25 13:56:39 +00:00
Martin Roth c45c2fb1f6 util/testing: Fully clean all but the standard GCC build
We don't currently use the artifacts from the Clang or CrOS GCC
builds, so don't bother saving them.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I69fe803e4b4213a199d0b76089da443aa769aa92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-25 13:55:27 +00:00
Eran Mitrani feed8e4bd9 soc/intel/adl/acpi: add FSPI to DSDT
A previous CL ("Add missing ACPI device path names",
commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors
from the Kernel on Brya devices (see Tim's comment on patchset 8):
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI

FSPI is defined in src/soc/intel/alderlake/chipset.cb:
device pci 1f.5 alias fast_spi on end

This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.

TEST=Built and tested on brya by verifying the error is gone.
BUG=b:231582182

Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25 13:54:24 +00:00
Werner Zeh 314f280aac commonlib/fsp_relocate.c: Fix cbfstool build on 32-bit host
On a 32-bit host, uintptr_t is defined as 'unsigned int' instead of
'unsigend long int' like on a 64-bit host. When cbfstool is built on a
32-bit host, the printk format specifier '%lx' expects a 'long int'
while new_addr is of type 'uintptr_t', aka 'unsigned int'.
This in the end leads to a build error.

To fix this and make it build on both, 32- and 64-bit hosts, use PRIxPTR
as the format specifier. This macro will be resolved at compile time in
the right way on both, 32- and 64-bit hosts.

Test=Build cbfstool on 32- and 64-bit hosts.

Change-Id: Ia917d2ed31778f3a29c0a6c7368f74c15319b099
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69682
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25 13:53:31 +00:00
Elyes Haouas a45ed44724 crossgcc: Upgrade IASL from 20220331 to 20221020
Changes: https://acpica.org/node/201

Change-Id: I386a6757a318336bc616091afe0c4ed88cd89583
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-25 09:52:18 +00:00
jimlai bbc8d912e8 drivers/intel/mipi_camera: Remove IPU ES support entry for RPL
The current IPU ES entry value is always set to true for RPL and
kernel picks the ES version of the main IPU FW even for the production
bootloader but loading is not successful due to the authentication
failure.

On Raptor Lake silicon, the production binaries are backward
compatible with ES parts.
This change removes the IPU ES support ACPI entry since the
kernel needs to load the production IPU main firmware on both the
ES/QS parts.

BUG=b:258125833
TEST=Verify the Camera functionality by enabling the IPU secure mode
on RPL variants with both ES/QS silicon.

Signed-off-by: Jim Lai <jim.lai@intel.com>
Change-Id: I9fd8ea0dd6ffdb16961bb017ba4388bf99e4d5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-25 01:03:21 +00:00
Elyes Haouas 8aebfd34d9 crossgcc: Upgrade MPFR from 4.1.0 to 4.1.1
Change-Id: I7679c6751fb02ab670ade923b365c6410a6dc118
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-11-25 00:59:37 +00:00
Martin Roth b357e53bff util/lint: Ignore fmd files when evaluating Kconfig symbols
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I5e3ff8ee10fdd3514033e72bd0c2664a4b2f5310
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-24 17:52:07 +00:00
Tim Crawford 705ebbea04 mb/system76: Reset Realtek codec before configuring
Perform a codec reset before configuring to avoid potential issues like
oryp5 had before 86f410479c ("mb/system76/oryp5: Reset HDA before
configuring").

Inspecting proprietary firmware for multiple boards shows that this is
always done as well.

Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66918
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-11-24 17:51:54 +00:00
Kapil Porwal c9cb8ff8fb drivers/wwan/fm: Use correct GUID for DmaProperty in ACPI _DSD
Use correct GUID for DmaProperty in ACPI _DSD.

Reference:
https://learn.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports

Before:
Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
{
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
    Package (0x01)
    {
        Package (0x02)
        {
            "DmaProperty",
            One
        }
    }
})

After:
Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
{
    ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
    Package (0x01)
    {
        Package (0x02)
        {
            "DmaProperty",
            One
        }
    }
})

BUG=b:259716145
TEST=Verified the new GUID is reflected in ACPI SSDT at runtime.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I05b8c3bf23cc43863527bc514d9a96096d45003c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-24 17:45:49 +00:00
Arthur Heymans 71e40782b8 google/*/*/sdram_configs.c: Add function argument
A function declaration without a prototype is deprecated in all versions
of C.

Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69748
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 15:17:58 +00:00
Martin Roth 8180427a16 soc/amd: Define post codes
For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.

picasso/romstage.c did get a couple of post codes removed to match the
other files.

The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.

Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-24 15:16:45 +00:00
Arthur Heymans 5e3798ca48 arch/arm: Use unified assembly syntax
Taken from Linux which also updated these files.

Clang only works with this syntax, so this fixes builds for arm.

TESTED on qemu vexpress-a9 and verstage on google/vilboz with
BUILD_TIMELESS=1, binaries remain the same.

Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63058
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 15:15:41 +00:00
Frank Chu a9921bcadb mb/google/brya/var/marasov: update pch_espi setting
Add conn0/conn1 for pch_espi.

BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69785
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 15:15:03 +00:00
Subrata Banik 98b696703e soc/intel/meteorlake: Decouple HECI disabling interface from its Kconfig
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.

BUG=b:260183610
TEST=Able to build google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3c9c5a73028cde90af3553093a13d0c05b831bae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69930
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:24:52 +00:00
Frank Chu fb43107e62 mb/google/brya/var/marasov: Add touchscreen and touchpad for marasov
Declare touchscreen and touchpad under I2C3 and I2C5

BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=Built successfully

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifc865fc0c0c42af0d74272289c562e347fac3a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69467
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:06:18 +00:00
Elyes Haouas d27b2e818b lint/checkpatch: Add XA_STATE and XA_STATE_ORDER to the macro declaration
This reduce the difference with linux v6.0-rc3.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ica20264d744ea8f77b56c63d29e1fafc2e68a869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-24 06:05:27 +00:00
Elyes Haouas 36d81dfbdb sb/intel/i82801gx: Move SPIBASE and SPIBARxx to i82801gx.h
Also remove unused DEBUG_PERIODIC_SMIS macro.

Change-Id: Ieb8487c7757b89a09c1cee4a83f94b9077dac87e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-24 06:05:08 +00:00
Elyes Haouas 9f0e21a4da sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros
Also, use {read,write}_pmbase16() in lpc.c file instead of inw/out.

Change-Id: Id281a3478051c4876ccbe26452d8744769c86654
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69878
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:04:40 +00:00
Mario Scheithauer 0f633f7f7f mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs
Set downshift counter to 2 for all Marvell PHYs on this mainboard before
the PHY downshifts to the next highest speed.

Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:04:03 +00:00
Mario Scheithauer 16dd1c31c2 drivers/net/phy/m88e1512: Add downshift enable
This patch provides the functionality to enable downshift on Marvell
PHY. By setting a downshift counter, the PHY is correspondingly often
attempted to establish Gigabit link before the PHY downshifts to the
next highest speed. The range is limited to 8 trials. To activate
downshift, a software reset must follow to take effect.

Change-Id: I4224eab6c1fc13824d53556c80435bc130a13bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69853
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:03:38 +00:00
Mario Scheithauer e19f403770 mb/siemens/mc_ehl2: Enable Marvell PHY interrupt
On this mainboard Marvell PHY INTn is routed to LED[2] pin.

Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:01:58 +00:00
Mario Scheithauer 155cf5cd2e drivers/net/phy/m88e1512: Add interrupt enable
INTn on Marvell PHY can be routed to LED[2] pin. This setting must be
made via LED Timer Control Register on page 3.

Change-Id: Ida1efbb604c382676b9d13ac8bf14de768f93637
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69433
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:01:30 +00:00
Mario Scheithauer 969531b6d8 mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver
This mainboard has three Marvel PHYs connected to the internal SOC GbE
controllers. The default LED status after HW reset of this PHYs shows a
different mode than what is needed. LED[2] is not connected on this
mainboard.

This patch sets the following LED status:
LED[0] - 7 = On - 1000 Mbps Link, Off - Else
LED[1] - 1 = On - Link, Blink - Activity, Off - No Link
LED[2] - not connected

TEST=Try different register values to verify LED feature.

Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69387
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:00:38 +00:00
Mario Scheithauer 1a97c89d7b drivers/net/phy/m88e1512: Provide functionality to customize LED status
For Marvel PHY it could be necessary to customize the shown LED status
at the connector. The LED status can be changed via Function Control
Register on page 3.

Link to the Marvell PHY 88E1512 datasheet:
https://web.archive.org/web/20221109080111/https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-phys-transceivers-alaska-88e151x-datasheet.pdf

Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69386
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:59:31 +00:00
Werner Zeh 49ec39fa7f device/mdio: Provide helper functions for read and write
This patch provides helper functions to read or write a register via the
MDIO bus. They can be used from drivers to easily access registers on
the MDIO bus.

Change-Id: I293d93435d27269a071b4b9b94a1b55307c575a7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69611
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:58:28 +00:00
Mario Scheithauer d4ab2ee38f drivers/net/phy/m88e1512: Add new driver for Marvell PHY 88E1512
This driver enables the usage of an external Marvell PHY 88E1512 which
should be connected to a SOC internal MAC controller. In a first step it
is only the framework of the driver. Functionality will follow with a
second patch.

Change-Id: I24011860caa7bb206770f9779eb34b689293db10
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69384
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:57:11 +00:00
Mario Scheithauer c16a7fc717 soc/intel/ehl: Add MDIO operation to TSN GbE device
This patch refactors the MDIO access for the TSN GbE device by placing
the MDIO read and write functions into mdio_bus_operations struct which
is assigned to the .ops_mdio member of the PCI device struct. In this
way the MDIO interface of the TSN GbE device is exposed and can be used
by other drivers if needed.

Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-24 05:56:37 +00:00
Mario Scheithauer 67f63e768d src/device + util/sconfig: Introduce new device 'mdio'
This patch extends the available device paths with a new device 'mdio'.
MDIO is the 'Management Data Input/Output' called interface which is
used to access an Ethernet PHY behind a MAC to change settings. The real
payload data path is not handled by this interface.

To address the PHY correctly on the MDIO bus, there is a 5 bit address
needed, which often can be configured via pins on the mainboard.
Therefore, the new introduced device has an 'addr' field to define its
address. If one wants to use a MDIO device in devicetree, the syntax is
straight forward (example):
	device mdio 0x2 on end

As the MDIO interface is driven by the MAC, most likely this MDIO device
will be hooked in as a child device of the (PCI attached) MAC device.

With the new introduced ops_mdio a new interface is added to provide an
API for read and write access over MDIO.

Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69382
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:53:55 +00:00
Kapil Porwal 66e44e3252 soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
This patch skips setting D0I3 bit for all HECI devices by FSP.

The learning being made from Alder Lake platform showed that the CSE
EOP cmd response time is highly nondeterministic and letting the EOP
cmd issued by FSP makes the response time even worse.

The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute
(late sending of EOP) to ensure there is ample time for CSE to come
to a state where the response to the EOP is almost immediate.

There were a number of refactoring being done to ensure the EOP cmd
can be sent at the later stage.

#1: Ensure FSP is not putting those HECI devices into the D0i3. (SoC specific change)
#2: Modify the CSE related boot state based operation to allow a
proper window for sending late EOP cmd. (Common Code Specific change)

The entire refactoring helps us to save ~60ms of boot time.

Without those code change EOP sending timestamp as below:

943:after sending EOP to ME                     1,248,328(61,954))

With those code change EOP sending timestamp as below:

943:after sending EOP to ME                     1,231,660 (2,754)

Port of commit d6da4ef69e ("soc/intel/alderlake: Skip setting D0I3
bit for HECI devices") to incorporate the #1 which is a SoC specific
code change.

BUG=none
TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
set to `1`.

Excerpt from google/rex coreboot log:
[SPEW ]   DisableD0I3SettingForHeci : 0x1

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-24 05:45:06 +00:00
Frank Chu 77c4d6165d mb/google/brya/var/marasov: Update SPD ID assignment
Adjust SPD ID order

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B	0 (0000)
H9JCNNNBK3MLYR-N6E		1 (0001)
MT62F1G32D4DR-031 WT:B		2 (0010)
H9JCNNNCP3MLYR-N6E		3 (0011)

BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3a62cf355508debce387c48d9d089e73763b2bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69784
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:28:50 +00:00