Commit Graph

38440 Commits

Author SHA1 Message Date
Arthur Heymans 3428027267 soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration
This prototype will be used outside of soc/amd.

Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 10:20:18 +00:00
Arthur Heymans 3967cf931b cpu/x86/smm: Add a common save state handling
Currently coreboot has limited use for the SMM save state. Typically
the only thing needed is to get or set a few registers and to know
which CPU triggered the SMI (typically via an IO write). Abstracting
away different SMM save states would allow to put some SMM
functionality like the SMMSTORE entry in common places.

To save place platforms can select different SMM save sate ops that
should be implemented. For instance AMD platforms don't need Intel SMM
save state handling.

Some platforms can encounter CPUs with different save states, which
the code then handles at runtime by comparing the SMM save state
revision which is located at the same offset for all SMM save state
types.

Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44323
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 10:20:07 +00:00
Arthur Heymans 7ac4722a35 cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4
The SMM_ASEG code only supports up to 4 CPUs, so assert this at
buildtime.

Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09 10:19:28 +00:00
Arthur Heymans a69d2c10a9 cpu/x86/smm/smihandler.c: Simplify smm revision handling
The ASEG smihandler bails out if an unsupported SMM save state
revision is detected. Now we have code to find the SMM save state
depending on the SMM save state revision so reuse this to do the same.

This also increases the loglevel when bailing out of SMM due to
unsupported SMM save state revision from BIOS_DEBUG to BIOS_WARNING,
given that the system likely still boots but won't have a functioning
smihandler.

Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09 10:19:18 +00:00
Jingle Hsu 4067fa3512 util/inteltool: Add support for Intel Lewisburg SKU C621A
Add support for dumping GPIOs on Intel Lewisburg SKU C621A.

Tested=On OCP Delta Lake DVT, verify it executes successfully.

Change-Id: I58797914aa5816aedace094c179e832150ad5e2e
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09 10:19:08 +00:00
Sridhar Siricilla c046dd0232 mb/intel/adlrvp: Replace if-else-if ladder with switch construct
The patch replaces if-else-if ladder with switch case for readability
purpose.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47054
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 10:18:22 +00:00
Matt Ziegelbaum 06bff726d4 hatch: Create genesis variant
Create the genesis variant of the puff reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:172620124
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_GENESIS

Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org>
Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-11-09 10:18:07 +00:00
V Sowmya a9a5dda093 mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvp
This patch adds the PMC MUX and CONx devices for adlrvp. Device
specific method contains the port and orientation details used
to configure the mux.

BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.

Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-09 10:17:35 +00:00
Marc Jones 662ac546fc soc/intel/xeon_sp: Don't add memory resource twice
The resource function is called for each device VID/DID. Only add
the memory resource map from the boot CPU (bus 0) and not for each
socket/CPU. This is a NUMA architecture and has a shared memory map.
All the resources must match across the sockets/CPUs, so they should
only be added to the map once.

Change-Id: Ia336f604441ae8d30b8418300da7c34ab9907cae
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-09 10:17:25 +00:00
Marc Jones 5851f9dae5 soc/intel/xeon_sp: Move set_bios_init_completion()
Move set_bios_init_completion() and helper functions from skx
and cpx soc_util.c to xeon common util.c. There are some slight
differences between skx and cpx, so used the more correct cpx
functions. Both cpx and skx platforms boot as expected.

Change-Id: Ie416b3a43ccdd14a0eb542786593c2eb4d37450f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47172
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 10:17:14 +00:00
Matt DeVillier 12d515dcc5 mb/purism/librem_cnl: Add new variant 'Librem Mini v2'
Add Kconfig entries, and update existing documentation to
accomodate both v1/v2 versions of the board.

Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:48:23 +00:00
Matt DeVillier 22f028a3c7 mb/purism/librem_mini: Fix USB_OC mapping in devicetree
Correct USB over-current mappings in devicetree now that the
GPIO config has been fixed per schematics.

Change-Id: I564630231933c7c17a2c0a2a403fdcca9189b92e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-09 07:48:14 +00:00
Matt DeVillier de10d8d609 mb/purism/librem_mini: drop PcieRpSlotImplemented from LAN PCIe
The LAN NIC is onboard, not installed in a slot.

Change-Id: I77ee7ee8c944b7942ca78d35cd881277c4030ab9
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09 07:48:06 +00:00
Matt DeVillier 0e4f37f7a7 mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
Add strings for M.2 keying and number of PCIe lanes.

Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:47:53 +00:00
Matt DeVillier e952392615 mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree
Correct PCIe clock source mapping in devicetree now that the GPIO
config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers
under their associated PCIe root ports.

Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-09 07:47:36 +00:00
Matt DeVillier 4d4256e499 mb/purism/librem_mini: Adjust GPIO pad config per schematics
- set pads GPP_B6/B8 for PCIe CLK_REQ lines
- set pad GPP_B14 to speaker output
- adjust comment for GPP_C22 / USB3_P1_PWREN
- set pad GPP_E4 to NF1 / SATA_DEVSLP0
- set pads GPP_E9/E10 to USB2_OC0#/USB2_OC1#

Change-Id: I8bf8af620370ec2d4c864e513db5d710a9c65d27
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47220
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:47:22 +00:00
Bryant Ou 0ee920bf64 console: Override uart base address
Add a new CONFIG_OVERRIDE_UART_FOR_CONSOLE token to override the index
of uart port, platform use a get_uart_for_console routine to decide what
index value should be used for console.

Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-09 07:46:10 +00:00
Arthur Heymans 12985c1dd7 soc/intel/xeon_sp: Look up the IIO_HOB only once
The HOB does not move, place its location in .bss.

Change-Id: I2c6dbe4d64138e45fa1dfe7580ffa70d0441bd88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47294
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:44:59 +00:00
Felix Held befec1e92e soc/amd/common: add Kconfig help text to pre-family-17h-only blocks
The cpu/car code only applies to pre-family-17h CPUs that still use
cache as RAM (CAR) and the PI code only applies to the pre-FSP vendor
code blob binaryPI interface.

Change-Id: I5a13d7e202bb745255fabb46110850c36b07de7a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47274
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:44:13 +00:00
Maulik V Vaghela 4a08736242 soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
In gpio.c file, we have community group array for each comm,
representing gpio groups within that community. Like there might be
group H,D, VGPIO and C within community 1. Community also may have
some reserved gpio and we also define those in an array which indicates
OS can't use those GPIO (through PAD_BASE_NONE)

Now when we define reserved pads in the middle of actual community
pads, it creates an issue while calculating an offset for GPIO
host own pad register. This is because function actually checks
current gpio index (lets say vgpio_39 in our case) and tries to get
group index from an array which we have defined. If we have defined
reserved gpios in between 2 communities, index calculated will also
account for reserved GPIO and register offset calculation will move
to next set of register (offset 0xC instead of offset 0x8).

Because of this coreboot won't configure HOST_OWN_PAD register correctly
and driver will not be able to get non-SMI interrupts for related gpio.

Align pad group as per EDS and pin-ctrl driver in linux kernel.

Reference: DOC#618876 (EDS volume 2)

BUG=None
BRANCH=None
TEST=VGPIO community index is correctly calculated. Drawlat board
boots fine with this change and warm reset also works.

Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-09 07:42:14 +00:00
Maulik V Vaghela e3f030ecbb soc/intel/jasperlake: Update reserved GPIO names in gpio_soc_defs.h
Multiple GPIOs were defined as a reserved GPIO in JasperLake. Correcting
this GPIOs with proper name to align with EDS volume 2

Also removing unused GPIOs at the end of community 4 (group E).
Since those reserved GPIOs are at the end of the community, it won't
affect the offset calculations within community. This change will also
help us aligning pad numbering with kernel pin-ctrl drivers too.

Reference: DOC#618876 (EDS volume 2)

BUG=None
BRANCH=None
TEST=Platform boots fine and basic functionality such as SD, Wifi works.

Change-Id: I8326b7181d47a177261656f51602638d8ce80fbb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:41:59 +00:00
Ricardo Ribalda 2b13ca5bcd mb/google/volteer/eldrid: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and the
gpio.

BUG=b:171888751

Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:41:37 +00:00
Ricardo Ribalda 43d0a7e66c mb/google/hatch/jinlon: Describe the privacy_gpio
Add information regarding the privacy pin on the overridetree and gpio.

BUG=b:169840271

Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:41:27 +00:00
Ricardo Ribalda df79757a3f drivers/usb/acpi: Add support for privacy_gpio
Some devices, such as cameras, can implement a physical switch to
disable the input on demand. Think of it like the typical privacy
sticker on the notebooks, but more elegant.

In order to notify the system about the status this feature, a GPIO is
typically used.

The map between a GPIO and the feature is done via ACPI, the same way as
the reset_gpio works.

This patch implements an extra field for the described privacy gpio.
This gpio does not require any extra handling from the power management.

BUG=b:169840271

Change-Id: Idcc65c9a13eca6f076ac3c68aaa1bed3c481df3d
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:40:52 +00:00
Sumeet R Pawnikar 8af39ff633 mb/google/dedede/variants/magolor: Update Power Limit2 minimum value
Update Power Limit2 (PL2) minimum value to the same as maximum value
for magolor board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.

BUG=b:168353037
BRANCH=None
TEST=Build and test on magolor board

Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09 07:40:26 +00:00
Tim Wawrzynczak 5145e23a35 soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-09 07:39:05 +00:00
Tim Wawrzynczak 8a78f59039 soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log
All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.

BUG=b:172279061
BRANCH=volteer

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-09 07:38:47 +00:00
Tim Wawrzynczak 8a1ad13822 device: Move pci_dev_is_wake_source function
Move this function to pci_ops.c, which is already included in the smm
build. This is required to use this function in elog functionality,
which is called from SMM.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie5583c04366c9a16bc1b00a6892d39eeafe5da49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-09 07:37:57 +00:00
Karthikeyan Ramasubramanian 3d4513e7c8 mb/google/dedede/var/boten: Add LTE power on/off sequence
LTE module used in boten has a specific power on/off sequence.
GPIOs related to power sequnce are:
* GPP_A10 - LTE_PWR_OFF_R_ODL
* GPP_H17 - LTE_RESET_R_ODL
1. Power on: GPP_A10 -> 20ms -> GPP_H17
2. Power off: GPP_H17 -> 10ms -> GPP_A10
3. Warm reset: Power off -> 500ms -> Power on
Configure the GPIOs based on these requirements.

BUG=b:163100335
TEST=Build and boot Boten to OS. Ensure that the LTE module power
sequence requirements are met.

Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:37:16 +00:00
Karthikeyan Ramasubramanian 2313e54bf9 mb/google/dedede: Add support for variant specific SMI sleep flow
This support is required to power off certain components that exist only
in certain variants.

BUG=None
TEST=Build and boot Boten to OS.

Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:37:01 +00:00
Karthikeyan Ramasubramanian 5eac877b75 driver/usb/acpi: Add power resources for devices on USB ports
Allow a USB device to define PowerResource in its SSDT AML code.
PowerResouce ACPI generation expects SoC to define the callbacks for
generating AML code for GPIO manipulation.

Device requiring PowerResource needs to define following parameters:
* Reset GPIO - Optional, GPIO to put device into reset or take it out
of reset.
* Reset delay - Delay after reset GPIO is asserted (default 0).
* Reset off delay - Delay after reset GPIO is de-asserted (default 0).
* Enable GPIO - Optional, GPIO to enable device.
* Enable delay - Delay after enable GPIO is asserted (default 0).
* Enable off delay - Delay after enable GPIO is de-asserted (default 0).

BUG=b:163100335
TEST=Ensure that the Power Resource ACPI object is added under the
concerned USB device.

Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46713
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:36:50 +00:00
Michael Niewöhner 835a2fa737 soc/intel/common/acpi: create pep.asl from lpit.asl
Copy lpit.asl to pep.asl to have a clean patch series without moving
files and to be able to keep the replace-patch CB:46471 as small as
possible to avoid confusion.

Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:35:38 +00:00
David Wu a944b547dc mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs
This change adds memory parts used by variant voema to
mem_parts_used.txt and generates DRAM IDs allocated to these parts.

Added memory
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E

BUG=b:171755775
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09 07:35:16 +00:00
Jakub Czapiga e0c60f3d39 tests: Add lib/timestamp-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I39abfc644fef085cef2175086a0e45a040b244de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-09 07:34:07 +00:00
Daisuke Nojiri 5742357e4d Atlas: Wake up AP on AC plug and unplug
This patch makes Atlas resume from S0ix by AC plug and unplug.

BUG=b:165328935
BRANCH=atlas
TEST=Put Atlas in suspend. Wake it up by AC plug.
TEST=Put Atlas in suspend. Wake it up by AC unplug.

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09 07:33:21 +00:00
Duncan Laurie 44caa1963f intel/common/pmc: Add functions for IPC mailbox in ACPI
This change adds two functions that provide an IPC mailbox method via
ACPI for runtime clock configuration.

pmc_acpi_fill_ssdt_ipc_write_method() will provide a method in the SSDT
that can be called by other ACPI devices to send an IPC mailbox command.
This function is exported because some SOCs override the default PMC
device and need to call this function to write the method into the SSDT.

pmc_acpi_set_pci_clock() will call the method defined by the previous
function to enable or disable the PCIe SRCCLK for a specified root port
and clock pin.  It can be called by the PCIe root port after turning off
power to the attached device.

BUG=b:160996445
TEST=boot on volteer device and disassemble the SSDT to ensure that this
method exists.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I95f5a1ba2bc6905e0f8ce0e8b2342ad1287a23a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46259
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:32:13 +00:00
Srinidhi N Kaushik 74c16d0a8b soc/intel/tigerlake: Utilize vbt data size Kconfig option
From Tigerlake FSP v3373 onwards vbt binary size changed from 8KiB
to 9KiB. Commit cf5d58328f had changed
the size from 8 to 9 Kib in drivers/gma. This change makes use of
Kconfig option to pick the size for tigerlake.

BUG=b:171401992
BRANCH=none
TEST=build and boot delbin and verify fw screen is loaded

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I21a0bba9ae01bac326f0f931641c98e8d308310f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:31:26 +00:00
Srinidhi N Kaushik 6719c82450 drivers/intel/gma: Add Kconfig option for vbt data size
From Tigerlake FSP v3373 onwards vbt binary size changed from 8KiB
to 9KiB. Commit cf5d58328f had changed
the size from 8 to 9 Kib. This change adds Kconfig option to choose
vbt data size based on platform.

BUG=b:171401992
BRANCH=none
TEST=build and boot delbin and verify fw screen is loaded

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ia294fc94ce759666fb664dfdb910ecd403e6a2e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47151
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:31:17 +00:00
Duncan Laurie ec2e3e479a acpigen: Add more useful helper functions
acpigen_write_debug_namestr() - Debug = NAME
acpigen_write_return_namestr() - Return (NAME)
acpigen_set_package_op_element_int() - Set package pointer element
 DeRefOf (PKG[ELEM]) = INT
acpigen_get_package_element() - Get package (not pointer) element
 dest_op = PKG[ELEM]
acpigen_set_package_element_int() - Set package element to integer
 PKG[ELEM] = INT
acpigen_set_package_element_namestr() - Set package element to namestr
 PKG[ELEM] = NAME
acpigen_write_delay_until_namestr_int() - Delay while waiting for
register to equal expected value.

BUG=b:160996445

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I9b20a23872b7d4a50f03761032426ffbb722b9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47196
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:30:01 +00:00
Karthikeyan Ramasubramanian 8e4182f20d mb/google/dedede/var/drawcia: Remove camera EEPROM power resource
EEPROM in the camera module does not require any specific power
resources. This will ensure that no unnecessary resources are turned on
while accessing the camera EEPROM.

BUG=b:167938257
TEST=Build and boot to OS in Drawlat. Ensure that the camera EEPROM is
listed in the output of i2cdetect.

Change-Id: Iece9b3f657bf94a21cc08bf1745353575858f9b2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:29:37 +00:00
Karthikeyan Ramasubramanian 65a9f4e78d mb/google/dedede: Enable Wake on AC connect and disconnect
Handle AC connect and disconnect notifications from Embedded Controller
(EC) and wake from S3/S0ix.

BUG=b:172266344
TEST=Build and Boot to OS in Drawlat. Ensure that the system wakes up
from suspend on AC connect and disconnect on both the TypeC ports.
276 | 2020-11-04 12:21:29 | S0ix Enter
277 | 2020-11-04 12:21:40 | S0ix Exit
278 | 2020-11-04 12:21:40 | EC Event | AC Disconnected
279 | 2020-11-04 12:21:57 | S0ix Enter
280 | 2020-11-04 12:22:03 | S0ix Exit
281 | 2020-11-04 12:22:03 | EC Event | AC Connected
282 | 2020-11-04 12:22:35 | S0ix Enter
283 | 2020-11-04 12:22:47 | S0ix Exit
284 | 2020-11-04 12:22:47 | EC Event | AC Disconnected
285 | 2020-11-04 12:23:08 | S0ix Enter
286 | 2020-11-04 12:23:16 | S0ix Exit
287 | 2020-11-04 12:23:16 | EC Event | AC Connected

Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:29:05 +00:00
Benjamin Doron 78e0acfb3e ec/purism/librem/ec.asl: End comment
End comment that (likely mistakenly) removed an EC query method.

Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-09 07:28:53 +00:00
Sumeet R Pawnikar 207ffb07fe mb/google/dedede/variants: Update Power Limit2 minimum value
Update Power Limit2 (PL2) minimum value to the same as maximum value for
dedede variants (baseboard and drawcia). Currently, variants like boten,
waddledee, waddledoo, metaknight and wheelie uses the DTT entries from
baseboard devicetree since there is no override present for these variants.
So, these variants will also reflect this change of PL1 minimum value.
For madoo variant, PL2 minimum value already set the same as PL2 maximum
value. DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.

BUG=None
BRANCH=None
TEST=Build and test on drawcia system

Change-Id: I7ecf1ffcc7871192ebe18eb8c3c3fd3e1193721e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:28:33 +00:00
Sumeet R Pawnikar 8e57299a0d mb/intel/jasperlake_rvp: Update Power Limit2 minimum value
Update Power Limit2 (PL2) minimum value to the same as maximum value for
jasperlake rvp board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.

BUG=None
BRANCH=None
TEST=Build and test on jasperlake rvp board

Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09 07:28:19 +00:00
Arthur Heymans ac12976f0c nb/intel/pineview: Fix clearing memory
The regions TSEG, GSM, GMS should not be marked as cacheable
resources.

Change-Id: I083b096cf3ed250bca722674abe9feffdb2436d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-09 07:28:01 +00:00
Patrick Rudolph 6e98292821 soc/intel/*/chip: Remove unused devicetree entry
InternalGfx isn't used so drop it.

Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09 07:27:38 +00:00
David Wu 2f6875518e mb/google/volteer/var/voema: config CSE LITE
Config voema to use CSE LITE

BUG=b:171755775
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09 07:26:56 +00:00
David Wu 25f3c4d083 mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema
BUG=b:171755775
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09 07:25:52 +00:00
Jes Klinke e94f86571c mb/google/volteer: Skip TPM detection except on SPI
Production Volteer devices have Cr50 TPM connected via SPI, depending on
Cr50 firmware version it may or may not support long enough interrupt
pulses for the SoC to safely be able to enable lowest power mode.

Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced
with Dauntless, communicating via I2C. The I2C drivers do not support
being accessed early in ramstage, before chip init and memory
mapping, (tlcl_lib_init() will halt with an error finding the I2C
controller base address.)

Since the Dauntless device under development can be made to support
longer interrupts, or a completely new interrupt signalling mode, there
is no need to try to go through the same discovery as is done via SPI.
This CL will skip the discovery, enabling the S0i3.4 sleep mode in all
cases, on the reworked test devices.

BUG=b:169526865, b:172509545
TEST=abuild -t GOOGLE_VOLTEER2 -c max -x

Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47049
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:24:54 +00:00
Karthikeyan Ramasubramanian d1c0f958d1 acpi: Call acpi_fill_ssdt() only for enabled devices
Individual drivers check whether the concerned device is enabled before
filling in the SSDT. Move the check before calling acpi_fill_ssdt() and
remove the check in the individual drivers.

BUG=None
TEST=util/abuild/abuild

Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-09 07:24:13 +00:00