https://qa.coreboot.org/job/untested-coreboot-files reports a bunch of
untouched Makefiles, so we never even attempt to build those tools.
Change-Id: I70ca658d9642b84fa8388c72ecb83327a6a74291
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch updates CPU microcode patch base address/size to FSP-S
UPD to have second microcode patch loaded successfully to enable
Mcheck flow.
This is new feature requirement for ADL as per new Mcheck initialization
flow.
BUG=b:176551651
TEST=Able to reach beyond PC6 without any MCE.
Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C
connections enter DP alt mode, which should wake the system from S3.
Configure S3 wake events to include MKBP so this actually wakes
the system.
BUG=b:174121852
BRANCH=zork
TEST=Generating DP event on MKBP via EC console wakes morphius
Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts
onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC.
BUG=b:170595019
TEST=Verify ezkinil still boots
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I1f5b6f535597149f28dd8c8322acc2e988f11505
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I1f07b5851ece6d0943faa9c90fc518805880a27d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49060
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Daniel Maslowski <info@orangecms.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built chili/base with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I5e2a09db80232457b2f78ad9b100c468d281f753
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built kontron/boxer26 with BUILD_TIMELESS=1, coreboot.rom remains the
same.
Change-Id: I08bd68aa2f98f93b8c5daf1ab2f3c1bbce521c53
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Ibc6833d9256800d0e50651cac18a4e81ddbe6895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48144
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move include directories from carriers and variants to mainboard level
being able to reuse them later. Also, rename guards so that they fit
their usage.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I55af05cb84b97d567ce1fc3b6151c34d1eda183f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48142
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All platforms moved to initialise GNVS at the time
of SMM module loading.
Change-Id: I31b5652a946b0d9bd1909ff8bde53b43e06e2cd9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48699
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI backlight support for boards selecting BOARD_GOOGLE_BASEBOARD_HATCH.
PUFF-based variants do not have an internal panel, so do not need this.
Test: build/boot Windows 10 20H2 on google/akemi, verify
display backlight controls functional.
Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49058
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts bit field macros to target PAD_CFG_*() macros. To do this,
the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/
gpio.h
This is part of the patch set
"mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values
CB:43858 - 2/3 Exclude fields for PAD_CFG
CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add functions to read the system and mainboard serial numbers
from VPD tables stored in flash.
Remove board-specific implementations for google/drallion and
google/sarien and select the new Kconfig instead.
Test: build/boot google/akemi with RO_VPD region persisted from
stock Google firmware, verify system/mainboard serial numbers
present via dmidecode.
Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49050
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, use of the VPD driver to read VPD tables from flash
requires the use of a custom FMAP with one or more VPD regions.
Extend this funtionality to boards using the default FMAP by
creating a dedicated VPD region when the driver is selected.
Test: build qemu target with CONFIG_VPD selected, verify entry
added to build/fmap.fmd.
Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The LPEA device memory resources, required by Windows drivers,
were not being set. Allocate required resources using
soc/intel/braswell/acpi/southcluster.asl as a reference.
This patch alone is not sufficient for working audio under Windows
on Baytrail ChromeOS devices, but it is a necessary component.
Test: boot Windows 10 on google/swanky, observe LPEA device working properly.
Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48745
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The (now removed) ID_SECTION_OFFSET=0x80 was actually the
secondary address flashrom and FILO are looking for. The
primary was 0x10, just below .reset.
If .id does not collide with .fit_pointer, use the higher
of the two locations.
Change-Id: I0d3a58c82efd3bbf94f4bc80ec5bbc97d5b1c109
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48499
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
intel_txt_memory_has_secret() checks for ESTS.TXT_ESTS_WAKE_ERROR_STS
|| E2STS.TXT_E2STS_SECRET_STS and it looks like with CBNT the E2STS
bit can be set without the ESTS bit.
Change-Id: Iff4436501b84f5c209add845b3cd3a62782d17e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47934
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New util directories have been added with no description.md file.
The description file for supermicro was added at a secondary level,
which doesn't help a user find the util since no path was added. Move
it up to the top level.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40b4c25dd7706513e96c6b8078a34160f8bb901e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
There's no need to use `memset` here.
Change-Id: I0478bc3ff25b75bf0b554aa83ead6a63fcbd975c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove index0 DRAM assignment since it doesn't use in any build.
Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id
BUG=b:175911098
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I853a316c266afafeecff67b263005a77be316e2b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48723
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PUFF-based Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.
Test: build/boot WYVERN variant, ensure boot splash/menu prompt visible
regardless of display init type used.
Change-Id: Ie6d2151d28058501498a4c501bb221919b4e1b39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
These Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.
Test: build/boot one of each variant, ensure boot splash/menu
prompt visible regardless of display init type used.
Change-Id: Ib90136b7e564451aff638af4d42abd97e42b3c19
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add struct i915_gpu_controller_info for boards to supply info needed
to generate ACPI backlight control SSDT.
Hook into soc/common framework by implementing intel_igd_get_controller_info().
Add Kconfig entries to set the correct register offsets for backlight
frequency and duty cycle.
Change-Id: Ia62a88b58e7efd90f550000fc5b2cef0cb5fade7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the panel settings dumped from vendor firmware and hook up
drivers/intel/gma, which will be required for brightness control.
Keyboard brightness control still requires ACPI code. This will be done
in a separate change later.
Test: Panel gets enabled when the payload starts on Clevo L141CU.
Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a new macro `GMA_DEFAULT_PANEL(ssc)` as shortcut for specifying one
internal panel at port A (0) in the devicetree.
Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move CPUID definitions out of msr.h into new cpuid.h header.
BUG=b:155307433
BRANCH=Zork
Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Instead of checking for an already fully build `libpayload.a`, we check
for the `libpayload.config` which is the actual prerequisite to start
using `lpgcc`. This will allow compilation of payload sources before or
in parallel with the build of `libpayload.a`.
Change-Id: Ic0143fefe33560af8b013ae48bbbe231b3ad46f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Introduce a `$_OBJ` variable, that points to the build directory for
in-tree usage of `lpgcc`. If unset, the default `../build` relative
to the location of `lpgcc` is used.
Change-Id: I35112d7533d69aa51252dd2bceec010a62522403
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47629
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This should make it easier to find the correct config for in-tree
builds.
Change-Id: I08d396ae3cedc65f63c4b8865701ea123c7d56cb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47628
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Keep libpayload's xcompile in its build dir. While we are at it,
align things with the top-level version.
Having `.xcompile` in a central place led to race conditions when
multiple payloads try to build their own libpayloads in parallel.
Change-Id: I504e1862db79b368289867f7568c9169f27a1549
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.
Always ensure that values don't overflow by applying appropriate masks.
The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For easier review of the switch to a new register struct in the
follow-up change, the panel delay times get converted from destination
register raw format to milliseconds representation in this change.
Formula for conversion of power cycle delay:
gpu_panel_power_cycle_delay_ms =
(gpu_panel_power_cycle_delay - 1) * 100
Formula for all others:
gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10
The register names gain a suffix `_ms` and calculation of the
destination register raw values gets done in gma code now.
Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.
Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.
BUG=b:168728787
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Patrick Georgi