Add new ram_id:1000 for memory part MT40A1G16RC-062E:B.
BUG=b:193732051
TEST=Generate new spd file and build coreboot.
Then boot from the DUT with new memory MT40A1G16RC-062E:B
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.
Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom
remains the same.
Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The configuration of the setting `chipset_lockdown` doesn't have any
effect for most of the variants since their configuration of
`common_soc_config` overwrites the configuration of the baseboard's
devicetree. If `chipset_lockdown` is configured separately in the
baseboard devicetree, the variant overridetrees reuse its
configuration.
Thus, move `chipset_lockdown` out of `common_soc_config` in the
baseboard devicetree and configure it separately.
Change-Id: I595c042cf62680d61f60965710d382bfdcd81671
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the part number for all boards was "Grunt". This patch adds the
correct part number/name for all variants.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If506df0b1027fb09f5027d8b9653b776fe3bdc75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55681
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure GPIO DGI_D4 (AP_XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:193499785
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: I21b7b811b8138cb3f71efecb0a0a886905c65a9c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
We may want to use that flash vendor on future variants.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To be able to enable & disable PSP_verstage in the saved .config file,
the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a
select to a default with a prompt.
BUG=182477057
TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK,
verify that VBOOT_STARTS_IN_BOOTBLOCK is set.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If two generic devices use the same number, device coming later
overrides the earlier device, as a result of this the static.c has
only one device.
In the case where we have UFC set to UFC_USB, this will result in
no IPU device scope in SSDT, since its entry will be set to disbled
after UFC probe.
TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change only enables the IOMMU device. We still require the IVRS
table to take advantage of the IOMMU. This will happen when the picasso
IVRS code is moved into common.
BUG=b:190515051
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need to reference correct USB port number for driver to
identify type-C port number correctly.
BUG=b:189476816
BRANCH=None
TEST=Check the transactions are happening on correct port. Also checked
retimer firmware update on both the ports.
Change-Id: I20c088ee81610155067abad086eba8d72f73ad60
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the kano variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:193052432
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KANO
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove register "generic.stop_delay_ms" and measure data, it still
can meet elan touchscreen specification that reset pull high to
I2C time > 150ms (T3 > 150ms).
BUG=b:185308246
TEST=Measure the T3 delay time is greater than 150ms on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56087
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the redrix variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192052098
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_REDRIX
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch sets the disable the external voltage rails since brya
board doesn't have V1p05 and Vnn bypass rails implemented.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR
detect condition for boten/botenflex sku.
BUG=b:186174768
TEST=build and test on boten/botenflex
Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
touchpad:390.4 kHz
BUG=b:192601250
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The caller is already passing the address to the required LTE reset and
enable GPIO. During memcpy, the address to that pointer is used which
will lead to copying undefined data. Fix the pointer/address used in
memcpy.
BUG=None
BRANCH=dedede
TEST=Build Kracko, Drawcia and Metaknight mainboards which use this
function.
Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Found-by: Coverity CID 1458053, 1458054.
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
brya0 is a reference and development platform, therefore it would be
helpful to have Crashlog enabled.
Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The brya EC supports S0ix hang detection, but it was not enabled in
coreboot as well, masking that event out of S0ix, therefore add it in to
the EC S0ix wake mask.
TEST=After EC prints "Warning: Detected sleep hang! Waking host up!",
the host actually wakes up
Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add SPD support to eldrid for DDR4 memory part MT40A512M16TB-062E:R.
Eldrid should use DRAM_ID strap ID 0 (0000) on SKUs populated
with MT40A512M16TB-062E:R DDR4 memory parts.
BUG=b:192380070
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4d07727c9c41bf494fbef373abce0ac1fc65c316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55983
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
P-sensor is swap by the latest schematic. Thus, swap the IRQ for correct
P-sensor.
BUG=b:192331122,b:181555900
TEST=check P-sensor driver can be probed without error.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3ccb31c1925e476e2ebb34b2439a491759472405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the cappy2 variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192035460
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CAPPY2
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I772801152b9ca9c2c6afe76a353cb2b62d6210ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
Reference CB:55348
BUG=b:191897776
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I63c912980530e5c9f341bdbab18c07685fd77abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add LTE modem to devicetree.
Configure GPIO control for LTE modem by fw_config.
Update LTE USB port configuration at run-time after probing FW_CONFIG.
By default the concerned USB port takes the Type-A port configuration.
BUG=b:186393848
TEST=Build image and check with command modem status
Change-Id: I20450ae37e5047dba67211316515994bd2a09600
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update LTE USB port configuration at run-time after probing FW_CONFIG.
By default the concerned USB port takes the Type-A port configuration.
BUG=b:178092096
BRANCH=dedede
TEST=Build and boot to OS to check LTE by modem status
Change-Id: If12cc29ddda6d5c32c0bda840a3680e7bf932f89
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54671
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf
BUG=b:191213263
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I3f6875ef438b147436605629445d346a56896a87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
set GPP_C3 and GPP_C4 as NC since LAN function removal.
BUG=b:190643562
Change-Id: I21214d0a2904ba4347fbbbc74237aca6db22c345
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55933
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
google_chromeec_get_event returns 0 for no event. Return
EC_HOST_EVENT_NONE=0 to improve readability.
BUG=b:184074997
TEST=Build and boot guybrush without error
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set GPP_B3 to APIC mode to avoid PCI IRQ conflict.
BUG=b:181555900
TEST=check dmesg there are no IRQ request errors like below.
genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1)
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To set the Fibocom 850-GL module to USB mode, it needs to be disabled
when PCIe training happens, or it will automatically switch to PCIe
mode. This patch makes sure it's shut down when training happens in
FSP-M. It will be brought up in ramstage and will be available for USB
enumeration later.
BUG=b:187316460
TEST=Run lsusb from the OS and see that the Fibocom module is present
on USB.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This configures the romstage portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.
The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe
devices out of reset, both need to be brought hign.
BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections. All available modules
are present after training.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures the bootblock portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.
Setting the PCIE Reset happens in coreboot instead of in the FSP.
The Aux reset lines are anded with the PCIe RST line, so both have
to be brought up together. On v1 of guybrush, the PCIe reset line
also resets EC communication, so it must be brought up immediately on
that version.
BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections. All available modules
are present after training.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add configs for Herobrine variants. Also enable ec sw sync as this
should not be disabled by default.
BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B
./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B
Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide
full range backlight settings to the kernel.
BUG=b:190443612
Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
1. Add 2 port 2 endpoint
2. Add support for OVTI5675
3. Guard entries in override device tree by FW_CONFIG
MIPI UFC is on I2C2
This configuration is as per P2 schematics
BUG=b:190674542
TEST=Build and Boot on Brya
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
When initializing eSPI early, guybrush has requirements to configure the
bus properly. Those are normally run in bootblock_mainboard_early_init,
but when setting up eSPI early, those have not run yet.
BUG=192100564
TEST=Build along with previous patch, eSPI works on guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
