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5747 Commits

Author SHA1 Message Date
Patrick Georgi 447cf563ca Fix building with relative path to object directory outside the source tree 
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 22:17:58 +00:00
Patrick Georgi 0c5b0642a9 iasl still can't cope with extra "." in file paths 
It's really a work around, but given how this issue seems to come
back again and again, let's work around it.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 22:16:49 +00:00
Patrick Georgi 96dafaf44d Fix ccache behaviour if more than one ccache in PATH 
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 22:14:07 +00:00
Scott Duplichan fb93178f13 Correct amd persimmon romstage code for early SPI prefetch enable. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 17:50:14 +00:00
Scott Duplichan 20aad25e6e Move the ACPI FACP table to the front of the RSDT list. This is done to work around a Windows XP or Server 2003 setup failure where an error message such as: "An unexpected error (805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c" occurs. This change updates AMD reference board projects, but could applied to others as well. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 00:06:09 +00:00
Patrick Georgi 6c44550df1 Move crossgcc rules to coreboot specific Makefile 
Toplevel Makefile should (as far as possible) be coreboot-agnostic,
we have Makefile.inc for that.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-16 15:32:28 +00:00
Cristian Magherusan-Stanciu 0b933d4644 Add crossgcc target to automatically build reference toolchain 
This means that a simple:

$ make crossgcc

creates the reference toolchain in the correct directory. Thanks to the
dependency on the clean-for-update target, an existing .xcompile along
with any compiled objects in build/ will be cleaned out, so the next
build will automatically use the newly created reference toolchain.

Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-16 01:35:03 +00:00
Peter Stuge 3f0075b3d2 cimx_wrapper/sb800: Fix indent in late.c:sb800_enable() 
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-16 00:05:50 +00:00
Marc Jones 44d3c3dade Remove multiple mmconf settings and just use kconfig setting. 
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 23:13:54 +00:00
Peter Stuge 16c8e37a2d agesa_wrapper: Avoid repetitive Kconfig depends, trivial 
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:40:40 +00:00
Scott Duplichan 8c46263721 Cosmetic cleanup. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:10:15 +00:00
Scott Duplichan 5d878ad312 1) Remove unused kconfig options. 
2) Correct UMA graphics PCI device ID.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:09:09 +00:00
Scott Duplichan a64ab46b62 Update gpp port configuration. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:07:56 +00:00
Scott Duplichan 769527e523 Enable rom cache early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:06:09 +00:00
Scott Duplichan 3c639e7df8 Fix memory allocation problem in amdInitLate. Disabled until further debug. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:05:00 +00:00
Scott Duplichan 0b886ae3c3 Remove some non-essential agesa options to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:03:45 +00:00
Scott Duplichan dbbbca3f33 Declare legacy video frame buffer so that Windows generic VGA driver will work. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:02:27 +00:00
Scott Duplichan 0ebefd27c8 Declare RTC as not PIIX4 compatible to match AMD hardware. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:00:23 +00:00
Scott Duplichan 254a6d6ea7 Make fadt revision match its length. Solves Windows 7 checked build assert. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:59:19 +00:00
Scott Duplichan b7e068305c Enable SPI cacheline prefetch early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:56:03 +00:00
Scott Duplichan 2cc5f550c7 Enable SPI cacheline prefetch early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:54:04 +00:00
Scott Duplichan d9a634c756 Switch processor cores to pstate 0 early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:51:31 +00:00
Scott Duplichan e73fc20886 Enable 33 MHz fast mode SPI read early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:48:22 +00:00
Scott Duplichan 9ab3c6c3a9 Build device paths for AP cores so that coreboot will report them to the OS. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:45:46 +00:00
Scott Duplichan be8fae1c71 Program the I/O APIC ID. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:41:00 +00:00
Scott Duplichan f191c72038 Enable AHCI mode and hide IDE controller to reduce boot time. 
Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios@seabios.org/msg00437.html

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:38:08 +00:00
Scott Duplichan dc312cca53 Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:26:04 +00:00
Scott Duplichan 2b9143afcc Fix ACPI shutdown function by removing reliance on SMI. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:19:54 +00:00
Scott Duplichan e78ae24eb1 Configure CIMx to use 33 MHz fast mode for SPD read. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:18:59 +00:00
Scott Duplichan 444c49c68c Match DIMM SPD addressing to implemented slots. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:13:00 +00:00
Scott Duplichan 6719c23a47 Size mmconf according to CONFIG_MMCONF_BUS_NUMBER. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:11:41 +00:00
Scott Duplichan b0b4063d6a 1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:10:20 +00:00
Scott Duplichan 6f7375c24c 1) Set I/O APIC ID according to BKDG recommendation 
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:07:43 +00:00
Scott Duplichan 6d6a456c9a Correct the number of MCA error reporting banks cleared. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:06:30 +00:00
Scott Duplichan a72425a7e6 1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization. 
2) Remove coreboot variable MTRR initialization because AMD reference code handles it.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:01:42 +00:00
Josef Kellermann eb97e9688f siemens/sitemp_g1p1: Adapt read_option() to latest changes 
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-13 06:25:16 +00:00
Patrick Georgi ceccd8dd67 Remove uart_init() in Siemens sitemp-g1p1 
uart_init() was moved to common code in r6531, but I
missed that when integrating the new mainboard code.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-12 06:53:52 +00:00
Josef Kellermann bfa7ee5b04 Add Siemens SITEMP-G1 board 
The code is loosely based on AMD dbm690t (and copied from there)
and adapted to match the Siemens SITEMP-G1 board.
It boots both Linux and Windows XP (and if it doesn't then complain
with me [Patrick] because in that case I must have messed it up when
integrating the patch)

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-11 07:47:43 +00:00
Patrick Georgi 8d6cf3a2d7 Work around unclean CMOS handling for now 
Stefan switched away from #ifdef across the tree (and is absolutely right with that), but
unfortunately there are some special cases that trigger in even more special situations.

Revert one such change selectively. It's destined to go once CMOS is reworked.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-11 07:44:27 +00:00
Patrick Georgi b251753b4f Change read_option() to a macro that wraps some API uglyness 
Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-10 21:53:13 +00:00
Vikram Narayanan 6649d9740d This replaces the fixed shift values in the apic timer init with macros. 
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-10 21:47:57 +00:00
Patrick Georgi a8f0f5120b Fix compilation error due to non-unix style line endings in cmos.layout file while generating option_table.h. 
Windows, Mac and *nix type line endings are now taken care of.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-10 21:42:52 +00:00
Ivaylo Valkov f2ed23f45b Adds RS740 HT and internal graphics PCI ids. 
Signed-off-by: Ivaylo Valkov <ivaylo@e-valkov.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-09 20:53:38 +00:00
Kerry She 6401fdb025 ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 platform. 
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-07 09:15:02 +00:00
Kerry She faafd14fe0 RS780 DDI Lanes configure support, 
and remove RS780 get_cpu_rev().

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-07 08:51:32 +00:00
Kerry She eb995c209c SB800 CIMX code can share the AGESA V5 lib code, 
some platform only use sb800 cimx code, not use AGESA v5 code.
for such platform, one can compile the sb800 cimx and AGESA v5 lib code.

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-07 08:43:40 +00:00
Kerry She 1c85c7794e 1. move _mm_clflush_fs() to __SSE3__ block, because __builtin_ia32_sfence() is the sse built-in function 
2. move the Amd Lib functions using sse build-in functions to __SSE3__ block

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-07 08:37:38 +00:00
Kerry She 8c4b499ba5 put the amdlib and agesa constant to .rodata segment. 
so amdlib.c would not complain "Do not use global variables in romstage"

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-07 08:33:14 +00:00
Frank Vibrans ccad951e7d Adds VOID to empty parameter lists to get rid of some build warnings. 
This change modifies a collection of files by adding the VOID parameter
to empty parameter lists to cut down on the number of warnings produced
when compiling the AMD Agesa code.  This should cut down the number of
warnings by about 1100 each for rom- and ramstage.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-05 16:49:11 +00:00
Frank Vibrans ec40260ade Remove AMD Agesa requirement for standard include files 
This change modifies Makefile.inc to add the -nostdinc flag to the default
CFLAGS value and removes the test for non-AMD Agesa builds.  Other code is
added to the gcc-intrin.h file in the Agesa Include folder to make the
requirement for the standard includes obsolete from the Agesa perspective.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-05 16:45:36 +00:00