Commit Graph

24784 Commits

Author SHA1 Message Date
Marshall Dawson 52f5cdce17 soc/amd/common: Add S3 supporting functions
Add functions that the wrapper will call to get and save the S3 data.
The wrapper requires two types of data saved:
 * Non-volatile:  Information that is the minimum required for bringing
   the DRAM controller back online.  This change uses the common
   mrc_cache driver to manage the storage
 * Volatile:  May be stored in DRAM; information required to complete
   the system restoration process.

TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064

Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12 16:59:58 +00:00
Matt DeVillier 047b23fc31 ec/chromeec: Fix battery ACPI mutex level
Commit 07fe618 [chromeec: Add support for reading second battery info]
added a mutex as part of the ACPI code to determine battery statuses.

Windows is extremely picky about ACPI code, and attempting to acquire
a level 1 mutex without first having acquired a level 0 mutex causes
Windows to hang on boot. Since there's no reason to use a level 1
mutex here, change it to level 0.

Test: Boot Windows on device with ChromeEC without hanging

Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-12 15:56:55 +00:00
Kevin Chiu 3be35976d6 google/snappy: enhance BigDaddy USB#2 2.0 strength
Fine tune 14" BigDaddy USB#2 2.0 strength:
PERPORTPETXISET: 7
PERPORTTXISET: 1
IUSBTXEMPHASISEN: 3
PERPORTTXPEHALF: 0

this value could have USB#2 2.0 EA/function pass.

BUG=b:72922816
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23649
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-12 03:54:23 +00:00
Lijian Zhao 1b64ae1119 soc/intel/cannonlake: Add Pch iSCLK programming
In order to reduce BOM cost and board area for imaging solution, the
sensor requires a 19.2/24MHz reference clock from PCH. In addition to
that, having PCH to supply the sensor reference clock will prevent
dependency on CPU power management and also avoid level shifter cost.

Pch iSCLK is only required for CNP-LP with the camera sensor on the
platform.

BUG=None
TEST=Boot up into OS and read back PCH iSCLK programming through
iotools.

Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23367
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-11 00:00:41 +00:00
Shelley Chen 106a9fe882 mb/google/fizz: Set SATA GPIOs in bootblock
Previously, we were seeing device boot into the recovery screen with
error code 0x5a.  This was root caused to the SATA GPIOs (specifically
DEVSLP) not being initialized early enough, causing the SATA 1 link
detection to time out and the device to reboot into recovery with
0x5a instead of booting into the OS as usual.

BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then type reboot from
     the OS.

Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-11 00:00:07 +00:00
Naveen Manohar f0b3a5fe4f mb/google/poppy/variants/nautilus: set oem_id, oem_table_id fields of acpi_header_t
This change makes the Nautilus platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.

BUG=b:68686020
TEST=Build, booted nautilus board. Verified kernel reads new strings.

Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/23648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10 23:58:57 +00:00
Lijian Zhao 3dd7d84c7c mainboard/google/meowth: Enable ECT again
Previously ECT was disabled in commit 22401, on D0 stepping system and
FSP version 7.x.20.52, disabling ECT will cause memory training failure
and the system is stuck at post code 00D5h.

BUG=b.72473063
TEST=Apply patch and build coreboot image, flash into meowth P0 system
with D0 stepping silicon installed, system can pass memory training and
boot up into OS.

Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-10 23:58:29 +00:00
Kaiyen Chang b924f40570 mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_t
This change makes Nami platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.

BUG=b:70646770
TEST=Verify kernel reads new strings.

Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://review.coreboot.org/23670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10 23:57:36 +00:00
Arthur Heymans 47dd96db97 payloads: Add an option to compress secondary payloads
Both GRUB and SeaBIOS can chainload lzma compressed payloads.
Therefore it is beneficial to compress secondary payloads
like Memtest86+, coreinfo, nvramcui,... for both size reasons and
often also speed reasons since the limiting factor is generally the
IO of the boot device.

Tested with SeaBIOS and memtest86+ master on Thinkpad X220.

Change-Id: Iddfd6fcf4112d255cc7b2b49b99bf5ea4d6f8db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-10 23:57:06 +00:00
Daniel Kurtz 9be42b5953 mb/google/grunt: Add ADAU7002 to devicetree
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S
converter.

BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
 **** List of PLAYBACK Hardware Devices ****
 card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
   Subdevices: 1/1
   Subdevice #0: subdevice #0
 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
   Subdevices: 1/1
   Subdevice #0: subdevice #0

Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10 23:56:44 +00:00
Daniel Kurtz 53b62130c9 drivers/adau7002: Add driver for handling ADAU7002
The ADAU7002 is a family of Stereo PDM-to-I2S/TDM conversion ICs from
Analog Devices.  On some boards they are a used to convert a PDM audio
data stream from a DMIC to an I2S signal.

Add a driver for populating ACPI table entries for this part.

BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
 **** List of PLAYBACK Hardware Devices ****
 card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
   Subdevices: 1/1
   Subdevice #0: subdevice #0
 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
   Subdevices: 1/1
   Subdevice #0: subdevice #0

Change-Id: I2b64c8e1cbc0a68984482a7d496f8c4498cb6cbe
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23659
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
2018-02-10 23:56:32 +00:00
Daniel Kurtz 76e9d6b1ac mb/google/kahlee: Add grunt audio codecs to devicetree
Remove manually written asl entries for grunt's DA7219 and MAX98357A
audio codecs, and replace them with equivalent devicetree entries.

BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
 **** List of PLAYBACK Hardware Devices ****
 card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
   Subdevices: 1/1
   Subdevice #0: subdevice #0
 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
   Subdevices: 1/1
   Subdevice #0: subdevice #0

Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-10 23:53:29 +00:00
Daniel Kurtz 2bfae02d1d drivers/i2c/da7219: Allow GPIO based interrupt
Allow specifying the DA7219 interrupt pin as either an Interrupt or
GpioInt.

BUG=b:72121803
TEST=(with whole patch series) Grunt Kernel discovers DA7219 on i2c0

Change-Id: I2d26731bf4c0ad590dad2c5d26c252371f415f9a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-10 23:53:16 +00:00
Martin Roth 681bf41087 util/broadcom/secimage: Add distclean target
When running 'make distclean' on coreboot, the build cleans the tools
as well. Since secimage didn't have a distclean target, it gave an error
that the distclean target didn't exist.  This didn't actually affect
anything more than the secimage clean, but it was impossible to tell
that from the warning:

% make distclean
make[1]: *** No rule to make target 'distclean'.  Stop.

Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10 23:49:58 +00:00
Martin Roth ba39770f2e soc/amd/stoneyridge: Put outl arguments in correct order
outl takes value then port.

BUG=b:72130849
Test=None

Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-10 23:49:42 +00:00
Lijian Zhao 2db6fbc47b chromeec: Fix ACPI compile warning
For system without secondary battery, current DSDT will report warning
during build time. Add a conditional check to make sure only battery
index 0 can return success.

TEST=Build pass.

Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-09 23:17:00 +00:00
Subrata Banik 6ee716e863 drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2.0 driver
As per FSP 2.0 specification and FSP SOC integration guide, its not expected
that SMBIOS Memory Information GUID will be same for all platform. Hence
fsp_find_smbios_memory_info() function inside common/driver code is not
generic one.

Removing this function and making use of fsp_find_extension_hob_by_guid()
to find SMBIOS Memory Info GUID from platform code as needed.

Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-09 06:03:00 +00:00
Lijian Zhao 93fde11aef soc/intel/cannonlake: Add support for EMMC DLL update
Add option to have customized DLL setting for EMMC interface to make
EMMC able to run at HS400 speed.

BUG=None

Change-Id: I38bc022d8c05dd1fbd03dc26aa6f33cd249e8248
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08 20:02:59 +00:00
V Sowmya 6b78b73d79 mb/intel/kblrvp: Enable Kabylake RVP8
Add support for KBL RVP8 board

* Add KBL RVP8 support in Konfig.
* Add KBL RVP8 config option in make menuconfig.
* Add descriptor and ME binary paths for RVP8 in Kconfig.
* Add RVP8 board name Kconfig.name.
* Add devicetree.cb for RVP8 in the variants path.
* Add gpio.h for RVP8 in variants/include/variant path.

TEST= Build and boot RVP8.

Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23383
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-08 20:02:32 +00:00
Gaggery Tsai 2a81fedd6a mb/google/poppy/variants/nami: Revise AC/DC loadlines
This patch revises AC/DC loadlines from VRTT reports.

+----------------+-------+-------+-------+-------+
| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
+----------------+-------+-------+-------+-------+
| AcLoadline     | 11    | 2.4   | 3.1   | 3.1   |
| DcLoadline     | 10    | 2.46  | 3.1   | 3.1   |
+----------------+-------+-------+-------+-------+

BUG=b:72351128 b:72129954
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings
     are passed to FSP.

Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-08 19:47:42 +00:00
Subrata Banik 54fa28efc3 soc/intel/skylake: Clean up SMBIOS Table Type 17 creation
* Add Memory Channel Status Enum for Channel detection.
* Align > 80 characters per line.
* Add hob_size == 0 check.

Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08 01:58:17 +00:00
Subrata Banik e8e432953d soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17
This patch ensures to have Type 17 SMBIOS table for CannonLake Platform.

TEST=Enable to get correct SMBIOS DIMM type information as per
SMBIOS spec 3.1

Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-08 01:58:01 +00:00
Shelley Chen 2a9e8124e1 mb/google/fizz: Set Pmax to 120 for all SKUs
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are
estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4
(71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) +
ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W.

BUG=b:71594855
BRANCH=None
TEST=Make sure correct pmax value is being passed into fsp

Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23633
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-02-07 20:41:37 +00:00
Akshu Agrawal dc4bc06bb7 google/kahlee/grunt: Fix 2 device specific variables
* micbias_lvl -> micbias-lvl
* mic_amp_in_sel -> mic-amp-in-sel

BUG=b:71875600
TEST=Checked in kernel the values are set

Change-Id: Ife7e8cdd835cc256cd8265593a94df84a510cebb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/23603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07 17:10:21 +00:00
Richard Spiegel d242892d4f mb/amd/gardenia: Remove cmos.layout
CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.

BUG=b:64207749
TEST=Build gardenia.

Change-Id: I24a71490777b101b069175460f3715ec3ff78240
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07 17:06:39 +00:00
Marshall Dawson 4c5a3b67e0 soc/amd/common: Add generic create_struct call to wrapper
Create a generic function that reports an unsuccessful call to
AmdCreateStruct().

Change-Id: I2654b4f21de5a2621086142681181a687be2c8e3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-02-07 16:39:50 +00:00
Nicolas Boichat c8fcc46025 mb/google/poppy/variants/poppy: Enable EC_ENABLE_SECOND_BATTERY_DEVICE
BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
     present, data is valid.

Change-Id: I869bf08341b83f359066709e1e9c03af99482b2c
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/23599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-07 16:38:21 +00:00
Nicolas Boichat 07fe6184bc chromeec: Add support for reading second battery info
We share the same shared memory fields for both batteries. When
the host wants to switch battery to read out, it will:
 - Set BTID (EC_ACPI_MEM_BATTERY_INDEX) to the required index
 - Wait for BITX (EC_MEMMAP_BATT_INDEX) to have the required value
 - Then fetch the data

BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
     present, data is valid.

Change-Id: Ib06176e6ab4c45a899259f0917e6292121865ed6
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/23598
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-07 16:38:14 +00:00
Marshall Dawson 857a387520 soc/amd/common: Improve misc. formatting in AGESA wrapper
Improve the file with:
 * C99 inializations for structures
 * reorder include files for aesthetics
 * remove extraneous whitespace
 * remove a stale comment
 * make variable naming consistent
 * make function arguments consistent

This change clears up all remaining checkpatch issues with the wrapper
with the exception of errors created with AMD definitions, e.g.
  ERROR: need consistent spacing around '*' (ctx:WxV)
  #32: FILE: src/soc/amd/common/block/pi/agesawrapper.c:32:
  void __attribute__((weak)) SetFchMidParams(FCH_INTERFACE *params) {}

BUG=b:62240746
TEST=Build and boot Kahlee

Change-Id: I40985e0cf50df6aa4d830937e7f6b6e7908f72fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07 16:37:39 +00:00
Marshall Dawson f3c57a7c28 amd/stoneyridge: Put stage cache into TSEG
Add a function to allow an external region to be located in TSEG.
Select the option to use memory outside of cbmem.  Increase the size
reserved in TSEG.

Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07 16:24:55 +00:00
Marshall Dawson 8d6e0e0a72 lib/stage_cache: Add save/get raw storage
Leverage the stage_cache mechanism to store a non-specific type
of data.  This is not interesting when the location for the cache
is in cbmem.  However it will be more useful when an external
location is used, e.g. when the cache is in TSEG, locked from user
modification.

Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07 16:22:40 +00:00
Subrata Banik ac1cd44525 soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig for CNP-PCH
This patch ensures soc/sata.c correctly translates pci config offset 0x92
Bit 0-2 [SATA Port x Present (SPDx)]
0 = Port x is enabled.
1 = Port x is disabled.

Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07 08:09:24 +00:00
Subrata Banik 828c39eb6b soc/intel/common/block: Fix SATA chipset register definitions anomalies
SATA PCH configuration space registers bit mapping is different
for various SOCs hence common API between SPT-PCH and CNL-PCH causing
issue.

Add new Kconfig option to address this delta between different PCH.

Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07 08:09:12 +00:00
Furquan Shaikh 9076b7bd07 mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to
match the latest schematic changes).

Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is
removed from deep_sx_config as well.

BUG=b:72697650
TEST=Verified:
1. Wake-on-wifi works.
2. Device is able to enter G3 without WAKE# pin causing unwanted wakes
from deep S5.

Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07 04:29:53 +00:00
Andrey Pronin 278a5064b4 security/vboot: overwrite existing spaces during factory init for tpm2
In TPM 2.0 case, if the factory initialization is interrupted after
defining, say, the kernel tpm nvram space but before writing to this
space, the following will happen upon reboot when the factory
initialization will be re-attempted. Writing to this space will be
skipped, and coreboot will finish the factory initialization with
this space remained unwritten. At a later stage, when the rollback
logic will attempt to check the version in the kernel space, it will
fail (TPM2.0 returns an error when reading from unwritten spaces),
and the system will go into recovery with no way out (since the
kernel space will never be written).

This change fixes that by always writing to the kernel, MRC hash and
firmware spaces during factory initialization, even if the space
already existed by that time.

BUG=b:71884828
TEST=delete, define, but not write to the kernel space; trigger
     factory initialization; coreboot should fill the kernel
     space and continue booting.

Change-Id: I48d8bb4f9fc0e5276e6ec81247b3b6768ec9fa3b
Signed-off-by: Andrey Pronin <apronin@google.com>
Reviewed-on: https://review.coreboot.org/23456
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2018-02-07 02:37:25 +00:00
Barnali Sarkar e962840282 storage: Fix CMD13 failure issue
This patch stores the correct capabilities for EMMC media which in turn
sets the correct timing data for HS400 mode.

Without this code change, EMMC CMD13 is failing at the end of HS400 mode
switching.

BUG=none
BRANCH=none
TEST=Build and boot Soraka

Change-Id: I3f00c9eace7cc136d86a1e07f040fbfc09e0e02e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23541
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07 01:48:24 +00:00
Barnali Sarkar f43adf0b89 intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES
This patch changes the sequence of post_cpus_init() function of mp_init
to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal
boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path.

Also, the fast_spi_cache_bios_region() call inside post_cpus_init()
function is left out, since caching the SPI Bios region is not required
now at this stage.

BUG=none
BRANCH=none
TEST=Build and boot in Soraka (KBL), executed stability tests on multiple
systems.

Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07 01:48:07 +00:00
V Sowmya acc2a4819c soc/intel/skylake: Add Kabylake PCH H device ID's
Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H.

Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23382
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07 01:47:51 +00:00
Arthur Heymans 742a0e911c nb/intel/sandybridge: Always use the same MMCONF_BASE_ADDRESS
'Optimizing' MMCONF_BASE_ADDRESS for the native codepath prevents the
use of fallback/normal with both the native raminit and the mrc.bin.

Using the same MMCONF_BASE_ADDRESS as the mrc.bin codepath means that
128MB less is available to devices using the native raminit. Most
devices reserve 2048M for non memory resources below 4G, which in most
cases is more than adequate. Devices with only 1024M (and that don't
already use the mrc.bin) are:
* lenovo/x220
* lenovo/x230
* lenovo/x131e
* lenovo/x1_carbon_gen1

Those could fail to allocate PCI resources, but on at least x220 with
a somewhat default configuration (USB3 expresscard, Wireless PCIe
card) it still boots fine, so one should not expect many problems from
this change.

Change-Id: I1d0648fe36c88bd9279ac19e5c710055327599fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-06 22:40:06 +00:00
Julius Werner 3f7411e198 google/gru: Add another 512KB to the COREBOOT FMAP region
With the new extra detachable UI elements, we're running out of space in
Scarlet's RO CBFS. Thankfully, the GBB is still massively
overdimensioned, so we can steal another half MB from there.

This patch changes the FMAP for some boards that have already had
production firmware releases. However, all the new changes are to the RO
parts of the FMAP, so there shouldn't be a way this could cause a
problem for updates.

Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06 19:47:21 +00:00
Vadim Bendebury 5542bb6531 soc/intel/skylake: sort CPU_SPECIFIC_OPTIONS and drop duplicate
ACPI_NHLT happens to be selected twice.

BRANCH=none
BUG=none
TEST=generated fizz .config does not change

Change-Id: Ic525ee07015deb88fff4c15cad9dbbeada8a4479
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/23601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06 16:17:17 +00:00
Alex Thiessen 457d1c8fa2 util/broadcom/secimage: Add HMAC test
One of responsibilities of the `secimage` tool is signing the image
using the HMAC-SHA256 algorithm. The test being added verifies that
secimage's internal call yields same result as the according openssl
tool does.

Change-Id: I8de4328f435af56901a861e3d5e733657c3c7f78
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06 16:14:33 +00:00
Arthur Heymans f300f36210 nb/intel/haswell: Use the common MRC cache driver
This driver uses an fmap region for the MRC cache instead of a CBFS
file which makes it easier to manage if one wants to write protect
it.

Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-06 16:13:49 +00:00
Arthur Heymans 485c0ad078 inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI
Tested to display the register content correctly on a Lenovo Thinkpad
X220.

Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-06 16:11:45 +00:00
Arthur Heymans 921fa84f9e inteltool: Fix displaying 64bit spi registers
The registers were taken from the wrong addess since the spibar offset
was not added to it.

This also fixes the endianness.

Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23478
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06 16:09:03 +00:00
Justin TerAvest ad282592b4 mb/google/kahlee: Fix grunt I2C rise/fall times
I2C bus rise/fall times were measured as follows. Signals were generated
with:
  - bus 0: manual i2c driver in depthcharge
  - bus 2,3: i2cdetect -r <bus_number>
and then measured manually with an oscilloscope.

BUG=b:72442912

Change-Id: I291e144249271ec34a93417398e54e68b8e21e23
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06 16:08:05 +00:00
Arthur Heymans f9d9781292 soc/intel/appololake: Remove dead MPINIT code selection
This not hooked up anywhere.

Change-Id: I95a2d14aea6f1a6013edf1bcb88bb35de88cba4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23458
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06 15:30:49 +00:00
Arthur Heymans 4004081e08 cpu/intel/haswell: Don't select PARALLEL_CPU_INIT
PARALLEL_CPU_INIT pertains to initialize_cpus() in
src/cpu/x86/lapic/lapic_cpu_init.c
which haswell does not use as it uses PARALLEL_MP init.

Change-Id: I46b6f72e8e372b8c8564243ece7aed3a9371c621
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-06 15:30:06 +00:00
Arthur Heymans 179a9048dd nvramtool: Fix message when option table is not found
Having an option table pertains to CONFIG_USE_OPTION_TABLE.

Change-Id: Ia8a84e3e59ee50444c7f7d17b34bea86ee475909
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06 15:29:30 +00:00
Richard Spiegel ddb4dcab8a soc/amd/stoneyridge/acpi/sleepstates.asl: Fix guarded code
Remove #if statement and replace it with if(IS_ENABLED(...)) per coreboot
recommendations.

BUG=b:62200858
TEST=Build kahlee.

Change-Id: I268b228706a625e1415c4f24e808261c279ba41e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-06 15:25:26 +00:00