Commit Graph

41191 Commits

Author SHA1 Message Date
Kyösti Mälkki 05af850b28 sb/amd/cimx/sb800: Move common OSFL method in ASL
We deal with mb/lippert/frontrunner-af later since it currently
does not include <cimx/sb800/acpi/fch.asl>.

Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:36:48 +00:00
Kyösti Mälkki 29b030dfcf AGESA,binaryPI boards: Drop OSV in ASL
Not referenced anywhere in ASL.

Change-Id: I52ac4722e48e1cc377386316dc034fb45a98181a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50471
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:36:14 +00:00
Kyösti Mälkki d591a5a328 ACPI: Move common _PIC method
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 21:35:47 +00:00
Kyösti Mälkki fa6a85c850 sb,soc/amd: Drop empty CIRQ call from _PIC
Change-Id: Iaa51e0530a3f72456d3d4e7a0c55b768ba63e322
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49904
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:35:11 +00:00
Kyösti Mälkki 3942a902cd sb/amd/cimx/sb800: Drop CIRQ method from _PIC
Change-Id: Ie4aad7b6580100377c12f128905f7f409bdb5295
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50590
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 21:34:22 +00:00
Kyösti Mälkki b57373b058 util/cbfstool: Fix build in 32-bit userspace
Fix regression from commit 0dcc0662f3 util/cbfstool: Introduce
concept of mmap_window.

Use of region_end() wraps around at 4 GiB, if utility is run in
32bit userspace. The build completes with an invalid coreboot.rom,
while one can find error message in stdout or make.log:

E: Host address(ffc002e4) not in any mmap window!

Change-Id: Ib9b6b60c7b5031122901aabad7b3aa8d59f1bc68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-14 20:59:37 +00:00
Felix Held 985f3e05e3 soc/amd/picasso/data_fabric: factor out common MMIO register defines
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I663a73308d33f48c6b945007f3eaac84d4712f59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50639
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:53:47 +00:00
Felix Held 602f93ed52 soc/amd/picasso/data_fabric: move more helper functions to common code
The number of data fabric MMIO registers is SoC-specific, so we need to
keep that in the SoC code. This also removes a redundant pair of
brackets and moves a loop counter declaration into the head of the loop.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:53:22 +00:00
Felix Held 0a1491366b soc/amd/picasso/data_fabric: use common access functions
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8cda860ca0ff81d7703c3277aeec629d89eab45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50622
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:53:08 +00:00
Felix Held 789f6f7c35 soc/amd/common/block/data_fabric: add data_fabric_broadcast_read/write32
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81e7ff293865ef22ed74606e1e79f67a460de4a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50621
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:52:53 +00:00
Felix Held 45df9c1b91 soc/amd/common/block/data_fabric: add data_fabric_write32
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c1ae03e9aec1dec45333e697060308cb6cbda4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50620
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:52:38 +00:00
Felix Held dba3fe7ad1 soc/amd/picasso: move data_fabric_read32 to common code
The exact same mechanism is used on Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 20:52:03 +00:00
Kyösti Mälkki 6962b6ecd3 sb,soc/amd: Move _PIC method to global scope
Fix regression with commit aa969e887a ACPI: Move PICM declaration.

While mentioned in the commit message there already, the default
value for AMD boards changed from IOAPIC mode to PIC mode.

ACPI 6.3 spec has this text regarding _PIC method:

  If the platform CPU architecture supports PIC mode and the method
  is never called, the platform runtime firmware must assume PIC mode.

If MADT has IOAPIC entries, OS will want to change to APIC model. But
the method _PIC was not in the global scope so it could not be called
and therefore _PRT continued to report PIC model interrupt routing.

Already fixed for soc/amd/picasso in commit 839f668.

Change-Id: I7f3bb0d45946cec315694de1d540fea4d828348e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-14 19:21:03 +00:00
Felix Held aed4aca3fc soc/amd/cezanne/chipset.cb: add SMBus and data fabric PCI devices
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica9b4adb1ec2b3663ce2d623cfe7b6539cd9c71b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50631
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 19:09:22 +00:00
Felix Held 65418cc8b5 soc/amd/cezanne: move CPU cluster to chipset device tree
This will be common for all boards, so move it to the chipset device
tree.

TEST=CPU cluster and LAPIC still show up in console logs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14 18:22:49 +00:00
Raul E Rangel ffdf840dbb mb/amd/majolica/mainboard: Set ACPI IRQ
We now pass the ACPI SCI IRQ to the OS, so make sure the board routes it
correctly.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1b4d5e0bfb1d9df9ac8a8c41cdf466a67f2673d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-02-14 18:15:56 +00:00
Raul E Rangel 12c6a58857 soc/amd/cezanne: Fill FADT and MADT
The MADT doesn't populate the IO-APICs yet since we need FSP to
configure those.

The FADT differs from picasso in the following ways:
* The duty_offset is supposed to be 0
* Don't clear x_firmware_ctl_l
* Make the extended addresses use MMIO

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 18:13:56 +00:00
Raul E Rangel 35dc4b0ede soc/amd/cezanne: Enable uCode update
TEST=Boot majolica and see microcode update
CBFS: Found 'cpu_microcode_blob.bin' @0x6900 size 0x15c0 in mcache @0xcf7fe9d8
microcode: patch id to apply = 0x0a50000b
microcode: being updated to patch id = 0x0a50000b succeeded

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If50b1d8b3ebf4b3e6f8a9dd3ab96073e0cb92424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 18:05:26 +00:00
Raul E Rangel 394c6b0922 soc/amd: Move update_microcode.c to common/block/cpu
We also want to support uCode loading on cezanne.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 18:05:17 +00:00
Elyes HAOUAS 844775059d superio/smsc/sch5545: Add missing <types.h>
Add needed but missing <types.h>.

Change-Id: I16c6a86e8c8863a8e16a63a379484c2b47d5185e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-13 22:06:28 +00:00
Raul E Rangel f5552cef97 include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS
This is a magic value that means all processors.
See Table 5-52 Local APIC NMI Structure in ACPI Spec 6.3.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic2fc060fda21bec44258bcae62ddb230be542759
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 21:54:54 +00:00
Felix Held 86024954df soc/amd/cezanne: select ACPI support and make the compiler happy
Follow-up patches will add more functionality.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 21:39:16 +00:00
Raul E Rangel 07acbfc6a5 soc/amd/common/acpi/gpio_bank_lib.asl: Add missing header
This file references ACPIMMIO_GPIO0_BASE.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic65a1f8759d10e7d78e30cfc82895e5af8cd83a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50571
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 21:38:53 +00:00
Raul E Rangel 984ecf9e74 mb/google/guybrush: Add plain dsdt
Needed to enable ACPI support for cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 21:38:30 +00:00
Raul E Rangel ec38e67d6c mb/amd/majolica: Add plain dsdt
Needed to enable ACPI support for cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifd71635d3493e0cf104b60ecf94ebdf70d512b94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 21:38:12 +00:00
Raul E Rangel 3ac44141ba soc/amd/cezanne/acpi: Add plain soc.asl
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I227cdb7cb4848d1d26f6d7fa13ac2cc1aea08d1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 20:58:57 +00:00
Felix Held 604ffa6d23 soc/amd: introduce and use common IOAPIC IDs
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.

Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 20:57:23 +00:00
Felix Held 5f5b7ddbf3 soc/amd/cezanne: always include PSP secure OS in amdfw
When USE_PSPSECUREOS isn't selected, we don't even get post codes on
Majolica, so remove this option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ec976f40d962a2d9f2bd36dc97d86526bd661ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-13 20:53:12 +00:00
Felix Held bb3e9ef507 soc/amd/cezanne: always add S0i3 firmware part to amdfw
Without this part being present in amdfw the PSP won't enter its normal
operation mode, but goes into recovery mode instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If13b5495e9f246afd0317daaa53c3d2cefbaa4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
2021-02-13 20:52:49 +00:00
Felix Held 2e1384aa47 soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry
Change-Id: I0b785abdd56af3bb67e3e36e5e3b40e544f0ca5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-13 17:09:11 +00:00
Kyösti Mälkki 84355a1aad mb/lippert/frontrunner-af: Use common sb800/acpi/pcie.asl
Change-Id: I6e6cdc49da540bd9901128bd1ef9f7060bc91f4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-13 14:52:36 +00:00
Angel Pons ec2ee184f7 sb/intel/bd82x6x: Clean up early_me.c cosmetics
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: I0dfbaaf4cb17841de109ea6abc08022846b5bd4e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 11:00:32 +00:00
Angel Pons 5152f16a2b sb/intel/bd82x6x/me_smm.c: Deduplicate finalisation code
The only difference between ME7 and ME8 is the MKHI message handling.
Remove duplicated code, and also clean up includes.

Change-Id: Ia44eb29d3509eb4208ba2aed9e0cf7e8f8d2c41a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49992
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 11:00:03 +00:00
Angel Pons 5deff30059 sb/intel/bd82x6x: Move ME SMM code into a separate file
This allows dropping some preprocessor usage. The `mkhi_end_of_post`
static functions had to be renamed to avoid a name clash. A follow-up
will tidy up the code in me_smm.c to reduce some duplication.

Change-Id: I6357fed3540be87f42d1fd59534666b9092d0652
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49991
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 10:59:49 +00:00
Angel Pons c94bc8e2d0 sb/intel/bd82x6x: Relocate some static functions
This allows us to get rid of the `__unused` attributes. Subsequent
commits will separate ramstage and SMM code into separate files.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: I1aaef5aa23561bee04f8dd9ddca66738bca91bb4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49990
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 10:59:30 +00:00
Kyösti Mälkki 505320375e sb/intel/bd82x6x: Use HPTS() for HPET visibility
Platforms with bd82x6x do not initialise OSYS, so HPET is
always hidden.

The two boards lenovo/x201 and packardbell/ms2290 using
sb/intel/ibexpeak but still including <bd8x62x/acpi/lpc.asl>
initialised OSYS using _OSI() method and showed HPET selectively.

Change-Id: I02fffd439be2a5a9d22afd67e68abce888361214
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49486
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:28:46 +00:00
Kyösti Mälkki 4797bb9be0 intel/broadwell,lynxpoint: Use HPTS() for HPET visibility
Platforms do not initialise OSYS so HPET is always hidden.

Change-Id: I5f030b156355ea407d37cdb2eda8a3161085436f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-13 06:28:32 +00:00
Kyösti Mälkki 9a05600004 sb/intel/i82801jx: Use HPTS() for HPET visibility
Change-Id: I741d94341ed59f5b5fbb8526205e8b502764a15a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50481
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:28:20 +00:00
Kyösti Mälkki e1738143e1 sb/intel/i82801gx,ix: Use HPTS() for HPET visibility
Change-Id: Id38228265ad89e3f96ea6f37bcc0da574a3f8c3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49484
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:28:02 +00:00
Kyösti Mälkki 4ff99a2655 sb,soc/intel: Add HPTS() for HPET visibility
Based on the detected OS the HPET ACPI device needs to
be hidden sometimes.

Change-Id: I4c6f87f30ea0de5c073b1fcf57794bb9e19d4d91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13 06:27:21 +00:00
Julius Werner a39c577257 trogdor: Add fingerprint power sequencing
Some Trogdor variants will include a fingerprint sensor, so this patch
adds support for its power sequencing. There is a requirement that the
fingerprint power needs to be *off* for at least 200ms, and when it is
turned back on it needs to stabilize for at least 3.5ms before taking
the FPMCU out of reset. We meet these timing requirements by splitting
the sequence across bootblock, romstage and ramstage. On current Trogdor
boards we measured <end of bootblock> to <end of romstage> at ~430ms and
<end of romstage> to <start of ramstage> at 12ms, so we easily meet the
required numbers this way.

BRANCH=trogdor
BUG=b:170284663

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-02-12 22:17:53 +00:00
Felix Held 43ccd6a4ad mb/amd/majolica/devicetree: add CPU cluster
Change-Id: I8d8b7f3ea2502e4e49a1290b07d84d5bbb2924a7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50506
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 22:03:31 +00:00
Felix Held 34fc29ae96 soc/amd: add and use fch_enable_hpet_decode
On Picasso we missed setting this bit in coreboot and since the default
after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge
and Cezanne have the HPET decode enable bit in the same position in the
same register. In the ACPI table entry written by
southbridge_write_acpi_tables the HPET entry gets added, so we should
make sure that we enable the decode.

TEST=HPET still works on Mandolin.

Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:49:10 +00:00
Felix Held 1b33205909 soc/amd/common: add and use fch_enable_ioapic_decode
The default value of this bit is 0, so set it right before calling
setup_ioapic to make sure that it's set and not to have to rely on FSP
doing the right thing.

Change-Id: Ife886451a6927965769282fc5644c2085abb9585
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50513
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:48:28 +00:00
Felix Held 428a682abe soc/amd/cezanne: drop PWRS from GNVS
A copy of Picasso's include/nvs.h was added to Cezanne right before the
commit d6ccbb9d48 that removed it for the
other mainboards and SoCs, so apply the equivalent change here as well
to keep everything in sync.

Change-Id: I76b551c05b3c3028a3afb3bc3b77df2401aed7a8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-12 20:47:35 +00:00
Raul E Rangel ffab5e64d1 soc/amd: Move MADT IRQ override settings into common_config
This is another common ACPI setting.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50558
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:59 +00:00
Raul E Rangel 1c88b10be2 soc/amd: Move fadt device tree settings into common_config
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:37 +00:00
Raul E Rangel 0e560e7015 soc/amd: Move acpi_fill_mcfg into common/blocks/acpi
This is common between stoney, picasso, and cezanne.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:45:17 +00:00
Raul E Rangel 0f3bc81210 soc/amd: Move southbridge_write_acpi_tables
This is common between all the chipsets.

It's also required by common/block/lpc/lpc.c.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12 20:44:48 +00:00
Raul E Rangel 48c99db6d6 mb/amd/majolica: Add FCH IRQ routing
I left most everything as NC since we don't expose the values to the
OS yet.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c3195ef27091f1bc61892c475ffe09137b63083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50511
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 20:43:09 +00:00