Commit Graph

41191 Commits

Author SHA1 Message Date
Kyösti Mälkki 639cc9c6ba soc/intel/baytrail,braswell: Sync PCI memory region in ASL
Baytrail had (only) occurence of DwordMemory vs DWordMemory.
Braswell one had bogus comments about the PCI memory range.

The actual region details are dynamically filled in _CRS.

Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02 14:50:01 +00:00
Elyes HAOUAS 00b5f53361 treewide [Kconfig]: Remove useless comment
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02 13:49:49 +00:00
Kyösti Mälkki 060ae5c88b soc/amd/common: Use only byte access for old GPIO
Change-Id: I06ec29845d051d9b90ab6f3cfb269ad5e6b75ea8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-01 22:43:32 +00:00
Elyes HAOUAS 38fa9f25ee soc/amd/picasso/fch.c: Remove unused <acpi/acpi_pm.h>
Change-Id: I5fea31f5893227a3e076c83a1759d3795b68c943
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-01 17:44:23 +00:00
Kyösti Mälkki ea1dd2e7a8 soc/amd/common: Drop ACPIMMIO GPIO bank separation
It's assumed in ASL already that the banks appear one
after other in ACPIMMIO space. There is no need for
the separation of accessor functions by name.

Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-01 15:21:51 +00:00
Kyösti Mälkki df84a28ccc mb/pcengines/apu2: Switch to proper GPIO API
Use the abstractions <gpio.h> provides.

Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-01 10:33:44 +00:00
Angel Pons b8a82496fe soc/intel/broadwell/gma.c: Add missing `break` in switch
Otherwise, the `GT_CDCLK_675` case falls through and exits early.

Change-Id: Icb979f8a980e1a1e1c712c5d9bc8d94c90376b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-01 09:05:34 +00:00
Yu-Ping Wu 39a84879f5 soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size
From the output of 'objdump -x dram.elf', the DRAM blob needs 222K
memory, but currently only 208K is reserved for it. Since MT8192 has 1MB
SRAM L2C, increase SRAM_L2C_END to 0x00300000, and reorganize regions in
SRAM_L2C to have larger DRAM_INIT_CODE (256K). The size of
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE is also increased to 252K.

BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Asurada booted successfully
BRANCH=none

Cq-Depend: chrome-internal:3568265
Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-01 09:04:48 +00:00
Angel Pons 3b7983a044 sb/intel/i82801ix: Factor out common `acpi_fill_madt`
It is the same for all three mainboards.

Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50027
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 09:04:25 +00:00
Angel Pons cf445ea89b sb/intel/common/rcba.h: Guard RCBAx macro parameters
Add brackets around the parameters to avoid operation order problems.

Change-Id: I689983b5b937f66b1a520eea61a38fb96c13c007
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50035
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 09:03:50 +00:00
Elyes HAOUAS 7d66b39513 soc/intel/skylake/Kconfig: Remove duplicated INTEL_DESCRIPTOR_MODE_CAPABLE
Change-Id: I15a1c17e870b04cc1238b54e4f69c227c877ca09
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-01 09:03:26 +00:00
Elyes HAOUAS 26c0e95394 src/soc/intel: Remove CPU_INTEL_COMMON_SMM selection
CPU_INTEL_COMMON_SMM is already selected in cpu/intel/common/Kconfig file.
Also remove duplicated 'CPU_INTEL_COMMON'.

Change-Id: I3328da567ac588e9bf6d57481fca117cc302a23a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-01 09:03:05 +00:00
Elyes HAOUAS 9660f06634 cpu/x86/name/name.c: Clean up includes
Also sort includes alphabetically.

Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 09:02:35 +00:00
Elyes HAOUAS a8817fc05f src: Remove unused <cpu/x86/smm.h>
Change-Id: Ic3f85a8fbc6a84074f45d94514e1dcfa78cb0958
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 09:01:35 +00:00
Elyes HAOUAS 77d3b655ed nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>
Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 09:01:00 +00:00
Elyes HAOUAS 487c1a24f5 nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>
Also replace 'reg' with 'reg32'.

Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49537
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 09:00:34 +00:00
Elyes HAOUAS 875c21f491 nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h>
Change-Id: Ib370fc1bae017d084844eece44799676a657323b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 09:00:13 +00:00
Elyes HAOUAS d73d19805e mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h>
Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45815
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:59:52 +00:00
Elyes HAOUAS 16d71173aa soc/samsung/exynos{5250,5420}/include/soc/cpu.h: Add missing include
Use of 'KiB' needs <commonlib/bsd/helpers.h>

Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44737
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:59:29 +00:00
Elyes HAOUAS c4d1b47ad9 nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>
Also rename 'reg' to 'reg32'.

Change-Id: Id741f636162a8a228bca069637993422deb5e09c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:59:10 +00:00
Elyes HAOUAS b96c358751 nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>
Also rename 'reg' to 'reg32'.

Change-Id: Ie8dd238a8f10daad9653f44b3ada329c3ede58fe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:58:56 +00:00
Elyes HAOUAS 9cbf26d18e nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h>
Also rename 'reg' to 'reg32'.

Change-Id: I3aca03dfe20dd0a61cba3ba55146f76e412a2c5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:58:39 +00:00
Elyes HAOUAS 9023eead66 mb/google/{butterfly,link,rambi,stout}: Remove unused <acpi/acpi_gnvs.h>
Change-Id: If5c35f3518e2cc4d5760a64e0d38fc4843af498a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50164
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:58:03 +00:00
Angel Pons 9b04f56d4a nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BAR
They aren't necessary. Removing them changes the binary because the
corresponding access macros no longer perform pointer arithmetics.

Change-Id: I9723a00b58ee35befdce6a3a51aa2b1fce8efa80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49745
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:56:08 +00:00
Subrata Banik cffc938934 soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC
and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip).

ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip).

Change-Id: I7d223c165f819669722cbc80245fa8ec20372352
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:55:34 +00:00
Eric Lai 1cf2427d1d security/vboot: Add config for GBB_FLAG_ENABLE_UDC
This change adds the missing `GBB_FLAG_ENABLE_UDC` as a config in
vboot/Kconfig (just like the other GBB flags) and uses its value to
configure GBB_FLAGS Makefile variable. This is done to allow the
mainboard to configure GBB flags by selecting appropriate configs in
Kconfig.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b397713d643cf9461294e6928596dc847ace6bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50110
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:55:22 +00:00
Angel Pons 42e4433ce0 bayhub bh720: Add helpers to access PCR registers
The BH720 PCR registers are accessed using an index/data register pair.
Introduce some helper functions to clarify the PCR register operations.

Change-Id: I1a48b10071af20dca61b7dd90c5a70bc9d1089b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-01 08:54:45 +00:00
Kyösti Mälkki 0b7446a269 sb/intel/i82801gx,ix: Drop MPEN from GNVS
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.

Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:54:31 +00:00
Kyösti Mälkki da321d8834 soc/amd: Drop PCNT from GNVS
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.

Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:54:23 +00:00
Ren Kuo 460b4f8dfd mb/google/dedede/var/magolor: Configure Acoustic noise mitigation UPDs
Enable Acoustic noise mitigation for magolor and set slew rate to 1/8
which is calibrated value for the board.

BUG=b:178678267
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Idea2a801399bb5c7e0b8e59ee7a826c86a44f4ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50099
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:53:57 +00:00
Frans Hendriks 1e9ea81a7f soc/intel/elkhartlake: Config PlatformDebugConsent
UPD PlatformDebugConsent field is not configured.

The config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT is available but not
used. Use this config value for PlatformDebugConsent.

BUG= N/A
TEST= Build Intel Elkhart Lake

Change-Id: I697fb611dfb23e107fa8ef1543424b9797a7d027
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50108
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:53:34 +00:00
Frans Hendriks f276079942 lib/asan.c: Update SPDX license
lint-000-license-headers reports error.
The SPDX identifier contains GPL-2.0

Update the identifier to GPL-2.0-only.

BUG = N/A
TEST = Build Intel Elkhart Lake

Change-Id: If49fd014f14b481163bca6cd3131139b6d95c6d8
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:53:22 +00:00
Erik van den Bogaert 246289c094 soc/intel/common/sata: Add support for Cannon Lake SATA (HALO)
Add device ID of Cannon Lake PCH-H Mobile HALO SATA controller
in supported device table.

Bug=N/A
TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully
completed

Change-Id: Ie1c2aa8273a53c47d7b3571394bcd85b59ab1142
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-02-01 08:52:42 +00:00
Erik van den Bogaert 7f501a36c6 include/device/pci_ids.h: Add Cannon Lake PCH-H SATA dev ID
Add SATA controller ID for Cannon Lake PCH-H Mobile HALO
(see document number: 571182)
Add SPDX license header

Bug=N/A
TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully
completed

Change-Id: Ic7e6ace2a24b4278b04caa58be907d38f4d117cd
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-02-01 08:52:34 +00:00
Arthur Heymans 3202c8afe4 console/console.h: Move get_console_loglevel() declaration
If for a stage __CONSOLE_ENABLE__ is 0, then there would be no
prototype for a get_console_loglevel() definition.

Change-Id: I805078921a5cc1506685f8aada3af5c5241260b7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50083
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:52:18 +00:00
Arthur Heymans cbce39005e drivers/security/cbnt: Fix bootblock size
Change-Id: Ic5ad9d29f247b6f828501bfacc27a8af08761d55
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-01 08:52:11 +00:00
Arthur Heymans 98872649c5 cpu/x86/mp_init.c: Print out the microcode revision of APs
It is useful to know if MCU have been applied successfully.

On the start of MP init lines similar to:
"AP: slot 1 apic_id 1, MCU rev: 0x0700001d" will be printed.
The example is taken from the log of an ocp/deltalake.

Change-Id: Ia0a6428b41d07f87943f3aa7736b8cb457fdd15a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49840
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:51:23 +00:00
Arthur Heymans 9daf5f071c cpu/intel/microcode: Reuse existing function to read MCU revision
Change-Id: If198fa68c0a29f46906151e667d7b00e2a3ab00d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:51:15 +00:00
JingleHsuWiwynn 4330b961c4 arch/x86/smbios: Add Number Of Power Cords field to be overriden
For SMBIOS type 3, add function to override number of power cords

Tested=Exectute dmidecode -t 3 to verify.

Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I7dee3a944a49ffcfdc2f4408d92a17aa39761bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:50:48 +00:00
Angel Pons f578b6f8f4 nb/intel/haswell: Calculate TSEG limit from registers
Done for consistency with other northbridges.

Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-01 08:50:24 +00:00
Angel Pons 849104f2fb nb/intel/haswell: Create RMRR for iGPU
Taken from Broadwell.

Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-01 08:50:08 +00:00
Angel Pons be6ad1ace0 sb/intel/lynxpoint: Use correct port mask for LPT-LP
Lynxpoint LP only has 4 SATA ports.

Change-Id: I565a0b2d29ac8fff8b5d87e0f1dbb3667f229365
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47035
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01 08:49:50 +00:00
Eric Lai 2a358fc52d mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01 08:49:26 +00:00
Furquan Shaikh 459d9e26dd mb/google/volteer: Select SOC_INTEL_CSE_LITE_SKU for volteer baseboard
This change moves the selection of SOC_INTEL_CSE_LITE_SKU into Kconfig
under BOARD_GOOGLE_BASEBOARD_VOLTEER instead of requiring each
individual board to select it.

TEST=Verified that timeless build does not result in any changes.

Change-Id: I2d94931fdc3077794bed5cc51708b5a5d9e64972
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01 08:49:07 +00:00
Furquan Shaikh 2d852cffb9 mb/google/volteer: Drop boldar variant
This variant never really got used and can be deprecated.

Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01 08:48:57 +00:00
Boris Mittelberg 93df61f3a9 mb/google/brya: Change EC -> PCH wake pin to GPP_F17
A new schematic revision indicates that the old wake pin is not used,
and brya will only use 1 IRQ pin from EC, routed to GPP_F17

BUG=b:178605367
TEST=Build test

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01 08:48:25 +00:00
Ricardo Ribalda fa21c922c6 Revert "mb/google/hatch/dratini: Describe the privacy_gpio"
This reverts commit f41645c34d.

In Dragonair, during the MP stage, one of the resistors needed
for this functionality has been removed. This results in the
privacy-switch not readable back by the system.

BUG=b:178458332

Change-Id: I0781f338d5ecd89fccee613fb13ea25c59385625
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01 08:48:16 +00:00
Johnny Lin 3acea5c51a ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocp
1. These are common OCP/Facebook IPMI OEM commands, move from mainboard
into drivers/ipmi/ocp to avoid code duplication and provide better
reusability.
2. OCP Tioga Pass enables IPMI_OCP driver.

Tested=On OCP Delta Lake and Tioga Pass verify the commands still work
correctly.

Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-01 08:47:48 +00:00
Elyes HAOUAS 8684643911 soc/amd/stoneyridge/acpi: Convert to ASL 2.0 syntax
Generated dsdt.dsl files are same.

Change-Id: Ife9bb37817815beec6dad4bc791abba4d91abe00
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-01 08:47:17 +00:00
Angel Pons 11fdb17564 soc/intel/broadwell/pch/sata.c: Don't enable Bus Master
Bus Master is not required and reference code does not set it.

Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-02-01 08:47:06 +00:00