Commit Graph

21069 Commits

Author SHA1 Message Date
Werner Zeh 27e6042bb7 intel/apollolake: Switch FADT to ACPI version 3.0
The current implementation of the FADT structure is only ACPI 3.0 compliant.
Setting the version to ACPI 5.0 results in a corrupt FADT. Linux seems
to be able to deal with it but Windows 10 hangs in a really early stage
without any notification to the user.

If ACPI 5.0 is mandatory, the FADT structure needs to be adjusted to
match the specification. Therefore the members sleep_ctl and sleep_stat
needs to be added to FADT structure.

Change-Id: I51c7a7a84d10283f5c2a8a2c57257d53bbdee7ed
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28 06:18:27 +02:00
Patrick Georgi 80656afc40 build system: when cleaning the tree, remove ..config.tmp*
kconfig uses mktemp so ..config.tmp isn't enough.

Change-Id: If910a40269783bbf7392b44cda7e9750bc33f14d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/19459
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-28 00:58:36 +02:00
Marc Jones d81250cebc amdfwtool: Move normal firmware 2 after fanless firmware2s
Move the images around in the image stitching. This addresses
an issue found with PSP firmware loading on the Google Kahlee
mainboard.

Note firmware1 must come before firmware2 in the image or
the PSP will not allow APU to execute.

Change-Id: I85963fa93d6efd707cedfbc04b92d302ad5de3b1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19170
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27 23:27:06 +02:00
Wei-Ning Huang 267e4a5824 mb/google/eve: switch touchpad devicetree to i2c-hid and cros_ec i2c device
The new touchpad firmware uses i2c-hid instead of custom reporting
protocol. The touchpad also exposed another slave address (0x1e) for
kernel to communicate with the touchpad EC.

Change-Id: Iecaf14f7b8aed836120569e9ade9c3115bc00264
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://review.coreboot.org/19461
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-27 22:26:01 +02:00
Marshall Dawson ca3815b4c5 cpu/amd/pi: Change wrapper to use config option
Add a check for vboot when locating the binaryPI image.

There is currently an ordering problem using cbmem to locate the
image when vboot is present.  Vboot inserts its locator into the
search process so that memory can be checked before flash is queried.
For the earliest calls using the wrapper, DRAM has not been set up
and cbmem not initialized in romstage.  This change prevents an
endless loop when vboot searches cbmem.

This change has another side effect.  When vboot is in effect, the
change forces the RO binaryPI to be used even when on either of the
RW paths.  There is currently no ability to relocate the XIP image
for use in a RW region.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474)

Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27 18:52:00 +02:00
Marshall Dawson 6f978cfd1a x86/acpi: Use initialized VBIOS in VFCT table
AMD VBIOS option ROMs often modify themselves during initialization.
Check for the presence of a VBIOS at 0xc0000 before populating the
VFCT table.  If a matching ROM is found, use it for the source of
the copy.

Tested on Gardenia (Stoney) variant by observing amdgpu driver's
dmesg output.

Change-Id: I5be7e1562bde51800c5b0e704c79812d85bcf362
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19383
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27 18:17:57 +02:00
Patrick Georgi 790aab6c77 crossgcc: fix DESTDIR builds
We need to rewrite libtool's files (foo.la) a couple of times so it
knows where to look
(while still whining that $DESTDIR$TARGET != $TARGET. well, duh.)

Change-Id: I54cafd47c76d855222ba905b5eb4533a23bdfd34
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/19463
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-27 18:11:25 +02:00
Shamile Khan bb368db2a4 google/poppy: Enable PD MCU device
In order for PD charge events to properly notify the OS when a charger is
attached we need to enable the PD MCU device and event source from the EC.

Without this change the charging still happens, but the OS does not notice
and update the charge state icon in the Chrome OS UI.

BUG=b:35586577
BRANCH=none
TEST=On a poppy board that has the VBUS rework applied, plug in a charger to
either port and see charge status updated to indicate charging in the
power_supply_info tool and the Chrome OS UI.

Change-Id: I59dcfc1cb5d11841f56cac7f4ffe461c2f9ec52a
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/19441
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-27 18:02:01 +02:00
Marc Jones 956a58e4fe amd/pi/hudson: Add VBNV cmos reset option
If the mainboard supports VBNV, call init_vbnv_cmos() instead of
the normal init_cmos(). The VBNV version does some VBNV pre
and post setup around the normal init_cmos().

Change-Id: I34b02409019b945cd68c830e006e99338643f29c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19399
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-27 17:09:08 +02:00
Kyösti Mälkki a2b7bd859a i82801gx: Enable PCI-to-PCI bridge
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.

Since the LPC function claims the resources for IOAPIC, ROM and
low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI
configuration will not overlap those regions and does not hide
the resources mentioned in the original comment.

The bridge was disable in the following commit [1]

    commit a8e1168064
    Author: Stefan Reinauer <stepan@coresystems.de>
    Date:   Wed Mar 11 14:54:18 2009 +0000

        This patch contains some significant updates to the i82801gx component and will
        be required for a series of later patches. Roughly it contains:

but unfortunately it was not noted which system this caused
problems with.

[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6

Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/2706
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-27 10:23:03 +02:00
Arthur Heymans fb2f667da2 nb/amd/amdk8: Link raminit_f.c
For this debug.c needs to be linked too.

Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-27 10:18:28 +02:00
Shelley Chen c0f7a1b7d1 google/fizz: Configure HDMI HPD to use native function
BUG=b:37684299, b:35775024
BRANCH=None
TEST=reboot and ensure graphics are displayed through
     HDMI port.

Change-Id: I74a664b2d42f55adfa64f292f6ede4c956e16fbf
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19451
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-27 10:15:31 +02:00
Shelley Chen e8365aa283 google/fizz: Enable SATA on port 1
BUG=b:37486021
BRANCH=None
TEST=compile coreboot and make sure sda and sdb show
     up in /sys/class/block.

Change-Id: I11344a4a5fc7e5b5d907d25439f92744a5fb70da
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19450
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-27 10:15:20 +02:00
Kyösti Mälkki 771e8c114f Revert "amd/pi/hudson: Move ACPI IO registers"
This reverts commit e7394ca903.

Configuration register for ACPI PM base address is initially configured
inside the PI blob. Therefore, the value of HUDSON_ACPI_IO_BASE needs
to be the same as DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS used in the build
of binaryPI blob.

Change-Id: I36700e49e21cc675e8e22b06efffb40e9c1e4236
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19454
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins)
2017-04-27 01:23:49 +02:00
Arthur Heymans 0c0b79689a mb/intel/d510mo: Add romstage timestamps
Change-Id: I324edce44ad82217ac1fba177f4a0bb3c799308c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19426
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-26 16:34:05 +02:00
Arthur Heymans 58ab3bed82 mb/intel/d510mo: enable ACPI resume from S3
Replace ram_check with quick_ram_check, because ram_check is slow and
is destructive for dram content.

Change-Id: I5fb1bfe711549aabb6e597bda22848988a7e9cbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19416
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-26 16:30:21 +02:00
Arthur Heymans d2ca9d12dc nb/pineview/raminit: Don't do Jedec init on resume from S3
This is not needed.

Change-Id: Id19a00c1546b7a71d90aa8c7e43e6efde1e9fbbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19425
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-26 16:29:12 +02:00
Pratik Prajapati ebb7994263 mma: Make MMA blobs path SOC specific
MMA blobs are SOC specific (not board). So far MMA
is supported by big cores (SKL and KBL).

Change-Id: I922789a2a12d55360624dd6de15ab9f0bb5f0acf
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/19260
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-26 16:26:46 +02:00
Marc Jones 6fcaaef614 amd/pi/hudson: Add TPM decode to SPI function
Add a function to send the TPM decode to the SPI interface.
Enables use of SPI TPMs on Hudson mainboards.

Change-Id: I0e85ed92163e38eca6a55456708ab322d6a90d4c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19402
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-26 04:14:12 +02:00
Marshall Dawson c1f32336e6 amd/pi/hudson: Clean up whitespace in header files
Change spaces to tabs and do general whitespace cleanup.

Change-Id: I4a4ecd42f91c9c6015a4f065b7386b17523ac6d9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19401
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-26 03:51:32 +02:00
Marc Jones e7394ca903 amd/pi/hudson: Move ACPI IO registers
Move the ACPI IO registers from 0x800 to 0x600 to avoid the
IO space required by the Google EC, also at 0x800.

This shouldn't have any conflicts on other AMD systems.

Change-Id: Iac7388c15e899277fd506fb37965164488358335
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19171
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-26 02:23:11 +02:00
Marc Jones f962aa52d6 amd/pi/hudson: Add LPC IO decode enable function
Add a function to enable LPC IO decode AKA WideIO.
This can enable up to 3 regions, which may be 512 or 16
bytes wide.

Change-Id: I2bed3a99180188101e00b4431d634227e488cbda
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19160
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-26 02:21:53 +02:00
Julius Werner a915cea289 cbmem_console: Document known reimpementations of console structure/API
It turns out that there are quite a few other projects that can access
the CBMEM console by now. If we ever want to make another structural or
behavioral change to it, we need to know where these implementations are
so we can make sure they're all getting updated. Let's try to build a
comprehensive list in the file that should be the source of truth for
all (coreboot's own implementation).

Change-Id: Ia3d6a87230f5bfdde9d812bc7154e22880c1377a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19439
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-26 01:31:51 +02:00
Marc Jones dae95f0dfe amd/pi/hudson: Add GPIO get function
Add a basic GPIO get function.

Note that GPIO set, ACPI/GPE, and other features should come
in future commits. Future changes to be modeled on the other soc/
gpio functions.

Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19159
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25 22:41:39 +02:00
Marc Jones 4aad421e81 AMD Geode: Move conflicting mainboard_romstage_entry()
The silicon specific mainboard_romstage_entry() in amd/cpu/car.h,
which is used by all AMD silicon car code, caused a conflict.
Move the silicon specific defines to silicon header files. Also,
no longer include car.h in the romstage file.

Change-Id: Icfc759c4c93c8dfff76f5ef9a1a985dd704cfe94
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18769
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25 22:39:05 +02:00
Paul Menzel d06c51895e soc/intel: Unify `timestamp.inc`
These files are actually indentical, but unfortunately, the formatting
was changed without caring for the already present files. Fix that. Use
the license formatting where less lines are used.

The next step is to put that in a common location.

Change-Id: Iecb263b9d321a33e64988b315220893df2e0045c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/19423
Tested-by: build bot (Jenkins)
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-25 18:47:35 +02:00
Arthur Heymans 878c2de41b util/ectool: Dump ram by default
According to the comment above the default should dump the EC ram,
though is never reached since the variable 'write_addr' is not 0, but
initialized at -1.

Also removes brackets around one line statement below if to make
checkpatch.pl happy.

Change-Id: I390996b253f2f20682cd9ab2d4f560de6eccfc57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19152
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-04-25 18:46:04 +02:00
Arthur Heymans 2873a4aea4 util/ectool: Fix timeout on sending EC command
When setting output to verbose, it incorrectly reports that it times
out on every command.

TESTED on Thinkpad X60.

Change-Id: I24f05f0c165462d5ba2604c7e2fe139400683275
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19151
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-04-25 18:44:46 +02:00
Furquan Shaikh c0dbdf4c90 soc/intel/skylake: Fix the PCI ID for SATA controller
Update the PCI ID for SATA controller on Kaby Lake.

Change-Id: Id0b5e0366e04fbac6a57a15407f33f390a2a1856
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19395
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25 18:42:29 +02:00
Aaron Durbin 79f0741f81 soc/intel/skylake: use postcar stage for fsp 2.0
Utilize the postcar stage for tearing down CAR and initializing
the MTRRs once ram is up. This flow is consistent with apollolake
and allows CAR_GLOBAL variables to be directly accessed and no
need for migrating CAR_GLOBAL variables as romstage doesn't
run with and without CAR being available.

Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19335
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25 18:16:18 +02:00
Aaron Durbin 5e88c3b18a device: allow devicetree accesses in postcar stage
Change-Id: Ib6f8ee937c4f3d8e2c0ff3851a819077fa499ccc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19334
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25 18:15:14 +02:00
Aaron Durbin e4d7abc0d4 lib: provide clearer devicetree semantics
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:

1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST

The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.

Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25 18:14:38 +02:00
Aaron Durbin 4003950881 console: rework log level to not be reliant on ROMSTAGE_CONST
The console log level variable doesn't really rely on ROMSTAGE_CONST
proper. Instead, the mutability of the variable is based on the current
implementation of ROMSTAGE_CONST (__PRE_RAM__). As such directly
use that logic for the code. In addition, refactor the code to let
the compiler and linker optimize out accesses instead of using
the pre-processor.

Change-Id: I44bcc409266ef52b9be29f75efde73a6707a53f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19438
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-25 18:13:56 +02:00
Aaron Durbin 42bcd13c75 Makefile.inc: ensure cbfs-files-processor-struct has correct ccopts
The ramstage-c-ccopts variable needs to be double dereferenced
for the cbfs-files-processor-struct handler so all the ccopts
are included since the ramstage-c-ccopts is fully constructed
later by another function. Without this not all the flags
are present on the command line.

Change-Id: I5425b3c1f23d767c61f654dd287584403f85d719
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19380
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2017-04-25 18:13:09 +02:00
Caesar Wang 01cbe3b75a google/gru: change the sd power sequence
In the safety considerations, we should make sure the slot of SD is
enabled first, since we want to the power switch of corresponding is
powered up.

The different boards have the different power switch for sdmmc.
Some power switch IC need turn on delay for long time.

let's move the slot power of SD to romstage and avoid explicit delays
or per-board.

BRANCH=none
BUG=b:35813418, b:35573103
TEST=check the signal for children of gru, and boot up from sd card.

Change-Id: Id164e4c4c900c6b1ca0251fc27db4cd36c56f6ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea1b01cc13628033b85251dbb44407f075efdc85
Original-Change-Id: I48ab543143d3de9be46608fc12d78e09decf8d79
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/447076
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19430
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25 10:51:28 +02:00
Marc Jones 7e438af995 mainboard/amd/gardenia: Remove PMxEE write on S4 resume
Delete the write to PM register 0xee.  This register is not
listed in the current BKDG and S4 is not currently supported
on this APU.

NDA document #47517 "A55/.../A85X fusion Controller Hub Register
Reference Guide" provides some clues on the intent of this write.
This register has always been observed to power on with a value
of 0x08 so the write has no effect.

This should be revisited again when SMI and PSP fully implement
the support required for S3.

Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18494
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25 06:15:46 +02:00
Marshall Dawson efd077ac52 arch/x86: Add read64 and write64 functions
Create new functions similar to read and write of other sizes.

Change-Id: I35a08c498f25227233604c65c45b73b1c44fae1f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19394
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25 06:14:39 +02:00
Daniel Kurtz 8e055f8f53 google/oak: Enable dual DSI for rowan and the BOE 8-lane MIPI/DSI panel
Unlike other oak derivatives, Rowan uses an 8-lane BOE tv097qxm-nu0
MIPI/DSI panel that requires dual DSI support.

Rework oak display initialization to special case Rowan, which uses a
provided edid struct for its panel, special panel backlight sequencing
and needs to configure mtk_ddp and mtk_dsi to use dual dsi mode.

BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel

Change-Id: I136ba5bd1ab12c4ad92995e066fc6d6cf54d0898
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19389
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-25 02:37:26 +02:00
Jitao Shi b927fe1954 mediatek/mt8173: Add support for Dual DSI output
The MT817x display output pipeline can be configured to drive an 8-lane
MIPI/DSI panel using "dual DSI" mode.  For the "dual DSI" video data path,
the UFO block is configured to reorder the data stream into left and right
halves which are then sent by the SPLIT1 block to the DSI0 and DSI1
respectively.  The DSI0 and DSI1 outputs are then synchronously clocked at
half the nominal data rate by their respective MIPI_TX0/MIPI_TX1 phys.

Also, update the call sites in oak mainboard to avoid build breakage.

BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel

Change-Id: Id47dfd7d9e98689b54398fc8d9142336b41dc29f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19361
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-25 02:36:55 +02:00
Daniel Kurtz 2332adacaf google/oak: Use edid_set_framebuffer_bits_per_pixel
This helper function was introduced so that mainboards don't need
to manually fill in these struct edid fields.

BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel

Change-Id: Ic9404a786a28b314b710e037dcae776be4b584ca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19388
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-25 02:34:54 +02:00
Lee Leahy eef40eb2a9 drivers/storage: Add SD/MMC/eMMC driver based upon depthcharge
The SD/MMC support is broken into several pieces.  There are three main
data structures:
* sdhci_ctrlr - This is SDHCI controller specific and defined in
  include/device/sdhci.h
* sd_mmc_ctrlr - This contains generic controller management data and
  defined in include/device/sd_mmc_ctrlr.h
* storage_media - This contains the flash storage device management data
  and is defined in include/device/storage.h

The SD/MMC driver consists of several components:
* SDHCI controller code
  * bouncebuf.c
  * bouncebuf.h
  * pci_sdhci.c
  * sdhci.c
  * sdhci.h
  * sdhci_adma.c
  * sdhci_display.c
* Flash storage device support
  * mmc.c
  * mmc.h
  * sd.c
  * sd_mmc.c
  * sd_mmc.h
  * storage.c
  * storage.h
  * storage_erase.c
  * storage_write.c

Kconfig values enable various portions of the controller and storage
drivers to be built to reduce the overall size of what is included in
the final image.

Full read/write/erase operations are provided for those platforms which
want to take advantage.  It is also possible to build the driver to
perform initialization only.  By default, this driver is not included in
any platform, platforms must specifically select DRIVERS_STORAGE to add
the SD/MMC support.

After this patch is reviewed and merged, there are some additional
patches:
* Common CAR storage area - Use a predefined region of CAR to pass data
  structures between bootblock through to romstage.  This allows early
  stages to preform the SD/MMC device initialization and later stages
  to use the SD/MMC device without further initialization.  The example
  code initializes the SD/MMC device in bootblock and uses the SD/MMC
  device in romstage without further initialization.
* CBMEM ID - Add a CBMEM ID value for the data structures so that they
  may be passed from romstage to ramstage and eventually the payload.
  The example uses the SD/MMC device in ramstage without further
  initialization.
* Move the SD/MMC driver into commonlib
* Have libpayload build the SD/MMC driver from commonlib.  The intent
  is to pass the controller state to libpayload so that the SD/MMC
  device can be used without further initialization.
* On some platforms, have depthcharge use the commonlib SD/MMC driver


History:

Copy the SD/MMC driver from depthcharge revision eb583fa8 into coreboot
and make the following changes:

* Removed #include "config.h" from mmc.c, allow the lint tests to pass.
* Move include files from drivers/storage into include/device.
* Rename mmc.h to storage.h.
* Add the Kconfig and Makefile and make edits to get the code to build.
* Add support to initialize a PCI controller.
* Fix formatting issues detected by checkpatch.
* Fix data flow issues detected by checkpatch.
* Add the missing voltage (MMC_VDD_35_36) into the voltage mask.
* Rename the macros mmc_debug, mmc_trace and mmc_error to sd_mmc_*.
* Replace printf with sd_mmc_error.
* Add sdhc_debug, sdhc_trace and sd_error macros.
* Add Kconfig values to enable storage device debugging and tracing.
* Add tracing and debug support to the SDHCI driver.
* Allow SOC to override more controller features.
* Split out ADMA support.
* Move 1V8 support into SOC routine.
* Move HS400 support into SOC routine.
* Rework clock handling.
* Change all controller references to use ctrlr.
* Update the voltage handling.
* Update modes of operation.
* Move DMA fields into MmcCtrlr.
* Update bus width support.
* Change MMC_TIMING_* to BUS_TIMING_*.
* Rename MMC_MODE_ to DRVR_CAP.
* Move quirks into ctrlr->caps.
* Associate removeable with the controller.
* Statically allocate MmcMedia.
* Replace the SdhciHost structure with the MmcCtrlr structure.
* Split the code to support other SD/MMC controllers.
* Split out erase and write support.
* Update the code to be more consistent with the coreboot coding style.
* Only expose calling APIs.
* Divide up mmc.c into 4 modules: MMC, SD, storage card, common code.
* Update debug and error messages.
* Add partition support.
* Display clock frequencies once in MHz.
* Remove mmc_send_cmd, use ctrlr->send_cmd instead.
* Handle error from sd_send_op_cond.
* Allow mainboard to control delays around CMD 0.
* Support command logging.
* Mainboard may set delay after SD/MMC command.
* Display serial number with sd_mmc_trace.
* Remove cmd set parameter from mmc_switch.
* Display errors for timeout and comm errors.
* Add LED support.
* Move 64bit DMA flag into ctrlr->caps.
* Rework PIO transfer routine.
* Add HS200 bus tuning.
* Add support for HS400.
* Use same format for HS400, HS200 and HS52.
* Reduce storage_media structure size
* Add routine to update code pointers
* Add display of storage setup
* Display controller setup

TEST=Build and run on Reef and Galileo Gen2

Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19208
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-25 01:05:05 +02:00
Lee Leahy bb70c40f2e include: Add xmalloc, xzmalloc and dma routines
Add a Kconfig value to indicate coreboot builds.

Add prototypes and definitions for:
* dma_coherent
* dma_malloc
* xmalloc
* xzmalloc

Move prototype for memset into stdlib.h from string.h to eliminate build
breaks.

TEST=Build and test on Galileo Gen2

Change-Id: Ib2eb2ca143b0538bdd1863e628af4c1948bc0f8c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19207
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-25 00:52:03 +02:00
Vadim Bendebury c77259c4e5 google/oak: Support cr50 over I2C on rowan
This patch enables TPM2 using cr50 over I2C for the Rowan board, and
adds an mt8173 specific TPM IRQ polling function. The function relies on
the appropriate EINT input configured to trigger the ready status on
the rising edge.

The cr50 TPM is on I2C address 0x50.

The cr50 interrupt GPIO is also made available for use by depthcharge
via the coreboot tables.

BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
 configured to use IRQ flow control when talking to the Cr50 TPM.

Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19364
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-24 22:33:06 +02:00
Daniel Kurtz 50340f5480 mediatek/mt8173: Add EINT support
Add basic support to configure GPIOs to poll for external interrupts
(EINT).

BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
 configured to use IRQ flow control when talking to the Cr50 TPM.

Change-Id: I9d52591661a5a74ec1fd9a081f606f0a08a3a6ab
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19362
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-24 22:32:52 +02:00
Daniel Kurtz 732618975e drivers/i2c/tpm: Remove vendor.irq
The vendor.irq field was originally intended for use as the TPM 1.2
"command complete" interrupt.  However, all actual coreboot tpm drivers
and hardware use the vendor.status method of checking command completion
instead, and this irq field is not used.

Let's just remove this unused functionality to simplify the code.

BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
    "cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
    "cr50 TPM" and does not complain about lack of tis_plat_irq_status().

Change-Id: I994c5bfbd18124af9cb81d9684117af766ab0124
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19396
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-24 22:32:22 +02:00
Daniel Kurtz 9164e37e98 mainboard/google/reef: Remove DRIVER_TPM_I2C_IRQ
DRIVER_TPM_I2C_IRQ has been removed.  TPM_TIS_ACPI_INTERRUPT now specifies
the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine.

BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
  "cr50 TPM".

Change-Id: If66a2a1d461a411e112589c84a434066d48b9399
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19410
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-24 22:32:06 +02:00
Daniel Kurtz d1329fe167 mainboard/google/eve: Remove DRIVER_TPM_I2C_IRQ
DRIVER_TPM_I2C_IRQ has been removed.  TPM_TIS_ACPI_INTERRUPT now specifies
the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine.

BRANCH=none
BUG=b:36786804
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
  "cr50 TPM".

Change-Id: Ia1eacd15e71a46a37457ee2f117b156393c3393d
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19409
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-24 22:26:41 +02:00
Daniel Kurtz c4852e7157 drivers/i2c/tpm/cr50: Use tis_plat_irq_status for Cr50 IRQ status
The Cr50 TPM uses an IRQ to provide a "status" signal used for hand-shaking
the reception of commands.  Real IRQs are not supported in firmware,
however firmware can still poll interrupt status registers for the same
effect.

Commit 94cc485338 ("drivers/i2c/tpm/cr50: Support interrupts for status")
added support for the Cr50 driver on X86 platforms to use a KConfig file
to supply an IRQ which it would poll using acpi_get_gpe.  If the IRQ is
not supplied, the Cr50 driver inserts a 20 ms wait.

Unfortunately this doesn't work so well when using the i2c connected Cr50
on ARM platforms.  Luckily, a more generic implementation to allow a
mainboard to supply a Cr50 IRQ status polling function was solved for SPI
connected Cr50s by commit 19e3d335bd ("drivers/spi/tpm: using tpm irq to
sync tpm transaction").

Let's refactor the i2c c50 driver to use this same approach, and change
eve and reef boards to make use of DRIVER_TPM_TIS_ACPI_INTERRUPT for
specifying the TPM flow control interrupt.

This essentially reverts these two commits:

48f708d199 drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe
94cc485338 drivers/i2c/tpm/cr50: Support interrupts for status

And ports this commit to i2c/tpm/cr50:

19e3d335bd drivers/spi/tpm: using tpm irq to sync tpm transaction

As a side effect the tpm_vendor_specific IRQ field goes back to its
original usage as the "TPM 1.2 command complete" interrupt, instead of
being repurposed to hold the flow control IRQ.

BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
    "cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
    "cr50 TPM" and does not complain about lack of tis_plat_irq_status().

Change-Id: I004329eae1d8aabda51c46b8504bf210484782b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19363
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-24 22:15:59 +02:00
Daniel Kurtz ed644b1803 mainboard/google/reef: Add TPM_TIS_ACPI_INTERRUPT
TPM_TIS_ACPI_INTERRUPT specifies the TPM2 ACPI interrupt used by intel's
tis_plat_irq_status() routine.

BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
  "cr50 TPM".

Change-Id: Ic69add8a3ce35be64fb37db4ed40163f6144fc9c
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19408
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-24 22:15:44 +02:00
Daniel Kurtz 7d4f70f76f mainboard/google/eve: Add TPM_TIS_ACPI_INTERRUPT
TPM_TIS_ACPI_INTERRUPT specifies the TPM2 ACPI interrupt used by intel's
tis_plat_irq_status() routine.

BRANCH=none
BUG=b:36786804
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
  "cr50 TPM".

Change-Id: Ifeb09a0a35bff7cd9091f6d027f0065288ca35c9
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19407
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-04-24 22:15:33 +02:00