Commit Graph

18953 Commits

Author SHA1 Message Date
Antonello Dettori b0a60e5b21 northbridge/amd/amdht: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdht.

Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16468
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:17:31 +02:00
Antonello Dettori 0501ece181 northbridge/amd/amdk8: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdk8.

Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16467
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:17:17 +02:00
Antonello Dettori f65ccb2cd6 northbridge/amd/amdfam10: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdfam10.

Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16466
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:17:02 +02:00
Antonello Dettori 30d55bf001 mainboard/bcom/winnetp680: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/bcom/winnetp680.

Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16465
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:49 +02:00
Antonello Dettori ef8021cc1b mainboard/gigabyte/*: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/gigabyte/*.

Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:35 +02:00
Antonello Dettori 837618bf20 mainboard/asus/*: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/asus/*.

Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:24 +02:00
Hakim Giydan e889b19ba0 soc/marvell/mvmap2315: Add DDR driver
This driver is only a prototype driver, real driver
will be integrated at a later time.

Testing: booted successfully.

Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16554
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:03:53 +02:00
Hakim Giydan f727c7ce38 soc/marvell/mvmap2315: Add MCU driver
Testing: booted successfully.

Change-Id: I003f6929b00476d46be931773cd35418fe6622a6
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15529
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:59:08 +02:00
Hakim Giydan 34c835db30 soc/marvell/mvmap2315: Add WDT driver
Testing: booted successfully.

Change-Id: Ie9c9297f321c838f86e5536aab29f67a0eeb053d
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15519
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:58:52 +02:00
Hakim Giydan 78785e7c41 soc/marvell/mvmap2315: Add NVM driver
This driver uses BootROM callback to read and write
to the nvm using I2C.

Testing: booted successfully.

Change-Id: I8639af3e004f6631d7e596507c106159835f979f
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:58:36 +02:00
Hakim Giydan 1bf8c4d443 soc/marvell/mvmap2315: Add A2BUS driver
A2BUS is a custom fabric.

Testing: booted successfully.

Change-Id: If6e61f5aa30217eb601ac460d9306166b8433569
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15523
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:58:20 +02:00
Hakim Giydan 5251a08d68 soc/marvell/mvmap2315: Add PMIC driver
Testing: booted successfully.

Change-Id: I168206585f403d2259efe424e563982be661df0b
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16149
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:58:01 +02:00
Hakim Giydan 53620b85be soc/marvell/mvmap2315: Add APMU driver
APMU is the AP power management unit.
It is a separate processor that handles enabling
individual power rails.

This driver handles sending and receiving commands
from/to APMU.

Testing: booted successfully.

Change-Id: I5ae07849f8432bece8a0ae9066a3f786e6e8d2fe
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15518
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:57:42 +02:00
Hakim Giydan 93e6f1a917 soc/marvell/mvmap2315: Add load_validate driver
Load_validate: it loads and validates images from
flash using hash values stored in the BDB.

Testing: booted successfully.

Change-Id: I0b00e8c60ed76622d03cb232d5c4273b4077aae7
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16148
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:57:23 +02:00
Hakim Giydan 6a1a36f7e9 soc/marvell/mvmap2315: Add flash driver
Testing: booted successfully.

Change-Id: Iaeff9f01dbfad7f313aa237e8c71c36c4ed1e06f
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15509
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:57:04 +02:00
Hakim Giydan 03d10ea29c soc/marvell/mvmap2315: Add gpio driver
Testing: booted successfully.

Change-Id: I89dee1bbf8b68460897f64bf673b328533e70cd4
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15508
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:56:43 +02:00
Hakim Giydan 65c7ccc8b1 google/rotor: Add support for the Rotor mainboard
Change-Id: I1f97b6f159a0ac36c96636066332ba355c056186
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15507
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:56:18 +02:00
Hakim Giydan 449368c2f0 soc/marvell: Add stub implementation of MVMAP2315 SOC
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.

Nvidia Tegra210 SOC and Rochchip Rk3399 SOC has been used
as templates to create this directory.

Change-Id: I8cc3e99df915bb289a2f3539db103cd6be90a0b2
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15506
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:55:53 +02:00
Werner Zeh 4f2754c720 fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode
The serial IRQ (SERIRQ) used by the LPC interface can operate either in
continuous or in quiet mode. Add a Kconfig switch to select the desired
mode. This switch can now be used on mainboard level to enable the
needed mode per mainboard.

Change-Id: Ibe246b88164a622f9c71ebe7bab752a083a49a62
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:52:53 +02:00
Werner Zeh 9d18e330fd siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC
Since this mainboard provides 4 COM ports on LPC, enable decoding of
the corresponding addresses using the generic LPC decode registers.

Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 22:41:45 +02:00
Elyes HAOUAS 6e8b3c1110 src/northbridge: Improve code formatting
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:08:19 +02:00
Elyes HAOUAS 6b72787d27 src/arch: Improve code formatting
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16434
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
2016-09-12 20:05:30 +02:00
Alexander Couzens c7702536ed Makefile.inc: build ifdtool using its own makefile
Change-Id: I67c73c101b928d104e231064e05d367bf9584730
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16571
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:04:33 +02:00
Alexander Couzens 746b6abea5 ifdtool/Makefile: use static dependencies
The generated dependencies doesn't work when
used together with our main build system.

Change-Id: I93d26858e961d7e275d586a1b8a26b3d33f3bd41
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16572
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:03:28 +02:00
Alexander Couzens d12ea11c01 ifdtool: fix one whitespace format error
Change-Id: I5b1846eb3ef8253695066b315e8a105803390579
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16570
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:01:24 +02:00
Arthur Heymans a761fa5ec9 lenovo/t60: add hda_verb.c
This creates a config for the Lenovo T60 sound card based
on values taken from vendor bios
(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16).
The sound card configuration on the vendor bios is the same
as the one on the Lenovo x60.

It improves the default behavior of the sound card:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker

Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-12 20:00:40 +02:00
Hakim Giydan 43e5b576b9 arch/arm: Add armv7-r configuration
This change adds armv7-r support for all stages.

armv7-r is an ARM processor based on the Cortex-R series.

Currently, there is support for armv7-a and armv7-m and
armv7-a files has been modfied to accommodate armv7-r by
adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants
to src/include/rules.h.

armv7-r exceptions support will added in a later time.

Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15335
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 19:58:43 +02:00
Rizwan Qureshi 06868f8154 kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.

Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:56:09 +02:00
Rizwan Qureshi d2ec56985f vendorcode/skylake: Add FSP header files without any adaptations
Add header files as is from FSP build output.
Move the FSP header files to new location as in apollolake.
Update all the FSP structure references now that they are
typedef'd.

Change-Id: I148bff04c064cf853eccaaaf7a465d0079c46b07
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16517
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:54:25 +02:00
Naresh G Solanki 55eee48b0e driver/fsp2_0: Include stdint header file in api.h
'bool' type is reported undefined due to missing stdint.h inclusion,
Fix it by including the same.

Change-Id: Ib09c121471bd8c490442330a478145a7d1d8855f
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16538
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:53:00 +02:00
Rizwan Qureshi e8c2e83973 arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrr
In the current implementation of postcar_frame_add_mtrr,
if provided size is bigger than the base address alignment,
the alignment is considered as size and covered by the MTRRs
ignoring the specified size.
In this case the callee has to make sure that the provided
size should be smaller or equal to the base address alignment
boundary.

To simplify this, utilize additonal MTRRs to cover the entire
size specified. We reuse the code from cpu/x86/mtrr/mtrr.c.

Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16509
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:52:27 +02:00
Rizwan Qureshi 8453c4f2fb cpu/x86: Move fls() and fms() to mtrr.h
Move the funtion to find most significant bit set(fms)
and function to find least significant bit set(fls) to a common
place. And remove the duplicates.

Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:51:36 +02:00
Rizwan Qureshi b1b44d34e3 arch/x86: Always compile postcar library in romstage
postcar_loader.c has a useful library of funtions for
setting up stack and MTRRs. Make it available in romstage
irrespective of CONFIG_POSTCAR_STAGE for use in stack setup
after Dram init.

The final step of moving the used and max MTRRs on to stack
is moved to a new function, that can be used outside of
postcar phase.

Change-Id: I322b12577d74268d03fe42a9744648763693cddd
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:50:18 +02:00
Venkateswarlu Vinjamuri d2e92e461d mainboard/google/reef: Enable lpss s0ix
This setting enables lpss to power gate in S0ix.

BUG=chrome-os-partner:53876

Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:49:28 +02:00
Venkateswarlu Vinjamuri 6584973bdc mainboard/google/reef: Disable CLKREQ of unused PCIe root ports
1. Removes PCIe blocker for S0ix.
2. Set the correct PCIe root port for wifi/bt on EVT.
3. Turn off CLKREQs of unused PCIe root ports to power gate the IP.

Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:49:08 +02:00
Werner Zeh 91aea428b5 fsp_broadwell_de: Correct access to SIRQ_CNTL register
The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.

Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 06:33:53 +02:00
Idwer Vollering ba349ab12e buildgcc: Quote command substitution
There are shells where the result of a command substitution is subject
to word splitting (e.g. dash when assigning a value inside an export
statement).

Change-Id: I70a5bc124af7ee621da2bdb4777f3eaba8adafbb
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/15820
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-09-11 14:27:42 +02:00
Antonello Dettori f9aac2f4ac southbridge/intel/i82801dx: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82801dx.

Change-Id: Ic08a23f672f8b5e40b837d49a9475d52c728a306
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16485
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:56:34 +02:00
Antonello Dettori 3c6bfaf8ca southbridge/intel/i82801ax: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82801ax.

Change-Id: I46f0cc92e1034f045988b42df7246f5d0c8d24fc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:56:19 +02:00
Antonello Dettori f068a73807 southbridge/intel/i82371eb: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82371eb.

Change-Id: Ie15a656c817a2ffe0f44ee3a89659d138a1bf212
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16483
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:56:04 +02:00
Antonello Dettori 4e1d9f6b23 southbridge/intel/i3100: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i3100.

Change-Id: Ic9616d5135cfb7206e086e51aaf82eb66540c4bb
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16482
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:55:52 +02:00
Antonello Dettori d3b55c1bb5 southbridge/intel/fsp_rangeley: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/fsp_rangeley.

Change-Id: I6665f85c74eb3e37d78f6eecbec977dc21a5ad12
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16481
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:55:38 +02:00
Antonello Dettori 60a6e153b0 northbridge/intel/x4x: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/x4x.

Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16472
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:55:22 +02:00
Antonello Dettori 1004710579 northbridge/intel/i5000: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/i5000.

Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16471
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:55:07 +02:00
Antonello Dettori 7ea0fe5cbf northbridge/intel/e7505: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/e7505.

Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16469
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:54:53 +02:00
Vaibhav Shankar e6a5f608e1 soc/intel/apollolake: Add functions to calculate GPIO address
Provide iosf and GPIO functions for GPIO address
calculation.

BUG=chrome-os-partner:55877

Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16349
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-09 23:51:01 +02:00
Philipp Deppenwiese 6e4204a0d1 util/release: Add support for signed tags and releases
* Add gpg key command-line parameter for signing.
* Add username command-line parameter for secure ssh clone.
* Tag and releases are signed.
* Generates ascii amored signature files.

Change-Id: I41347a85145dd0389e3b69939497fb8543db4996
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/16553
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09 23:39:42 +02:00
Damien Zammit 55a54f662e mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridge
Although the goal was to hide the ME device by disabling
the PCI bridge, the original comment that this bridge was ME related
was a mistake, this bridge is for PEG not for ME.
We still need this PCI bridge "on" to enable pci express graphics
add-on cards.

Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16496
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-09 19:40:34 +02:00
Antonello Dettori 305224f47a northbridge/intel/fsp_rangeley: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/fsp_rangeley.

Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16470
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09 18:54:56 +02:00
Damien Zammit 88af372fe8 nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfaces
Previously the ME PCI interface (HECI) was being reported as present in
the DMAR ACPI table even when ME firmware was missing or the PCI device
was hidden and HECI would be unresponsive.
Now we check via the PCI config space itself to verify if the HECI
is present or not.

Note that this test could fail if ME firmware is present but
HECI is disabled in devicetree, because it would not advertise that the HECI
exists even though there is a running ME.  Perhaps this behaviour is desirable
because in this case you won't see the HECI in the lspci tree anyway.

Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16330
Tested-by: build bot (Jenkins)
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-09 17:11:44 +02:00