Set tcc_offset value to 10 in devicetree for Thermal Control Circuit
(TCC) activation feature as mentioned in doc #572349.
BUG=b:229804441
BRANCH=None
TEST=Build FW and test on Nivviks board
Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Now that the FSP provides the ALIB ACPI table via a HOB, the PNOT power
notify method can call WAL1 which will then call ALIB to communicate the
current AC/DC state to the SMU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic966b73aa28f329207f8d840ca5fb5f2bf6ec9b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64667
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Skyrim uses the Ti50 GSC and the config should be updated to
reflect that.
BUG=b:233750667
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5d4af19ab2dda35ab687a0659898d79b08c4de97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable the USB port that is used by the Bluetooth interface on the CNVI.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2a330618c5f1c5fd5e3147cb6307c157b28070ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64545
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the Webcam USB port form the devicetree and handle it solely in
devtree, which will enable or disable it based on the CMOS option.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9c89c7103aca5c3d42215122e9d94c83947b6fee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Add Q60 and Q61 events to disable or enable the trackpad. The
support for this Q event was added in Star Labs EC version 1.11
Add Q events Q60 and Q61 which are bound to the F10 key. The event
is select based on the value of 0x14, 0x11 will send Q60 and 0x22
will send Q61. Q60 will pull GPIO_177 to low, consequently disabling
the trackpad and Q61 will reset it to the default configuration.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I091b0eb268d4d6d2109559765be71e2746b85f54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set tcc_offset value based on the power_profile value, ranging from 5
to 15 degrees.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id30bec9c095517884a7361226aed703b370f2207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Under the current watchdog setting, the system will not reboot when the
temperature is too high. To enable thermal hardware reset, we need to
enable thermal control request and set it to reboot mode.
Note that because thermal throttle (by lowering cpu frequency) is
currently enabled, the thermal hardware reset shouldn't be triggered
under normal circumstances.
This feature is only for new hardware structure for thermal. Therefore,
we only need to apply it on MT8192/MT8195/MT8186.
This setting is based on thermal and watchdog section of MT8192
Function Specification.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I98b062c2070384527624c3bcf0dfded25a2c8ce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64676
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Under the current watchdog setting, the system will not reboot when the
temperature is too high. To enable thermal hardware reset, we need to
enable thermal control request and set it to reboot mode.
Note that because thermal throttle (by lowering cpu frequency) is
currently enabled, the thermal hardware reset shouldn't be triggered
under normal circumstances.
This feature is only for new hardware structure for thermal. Therefore,
we only need to apply it on MT8192/MT8195/MT8186.
This setting is based on thermal and watchdog section of MT8195
Function Specification.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia6489bb953d148a43af173454d6f2b3e2a1dfcf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64675
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Under the current watchdog setting, the system will not reboot when the
temperature is too high. To enable thermal hardware reset, we need to
enable thermal control request and set it to reboot mode.
Note that because thermal throttle (by lowering cpu frequency) is
currently enabled, the thermal hardware reset shouldn't be triggered
under normal circumstances.
This feature is only for new hardware structure for thermal. Therefore,
we only need to apply it on MT8192/MT8195/MT8186.
This setting is based on thermal and watchdog section of MT8186
Function Specification.
BUG=none
TEST=emerge-corsola coreboot
TEST=thermal hardware reset is working.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: Id2ed55e6d4f4eec450bf7c849f726a389eeb6694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64659
Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are zero-initialized arrays within AGESA that were previously not
declared with CONST qualifier. Without this flag, such arrays would have
consumed valuable CAR space in romstage.
After adding CONST qualifiers these arrays have actually moved to
.rodata and removing the flag does not add anything to .bss.
TEST: see that BUILD_TIMELESS=1 results in the same binary.
Change-Id: I5b91deb1bf1b64bd9c88dc311db4e0b36df86c18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Now that all AGESA codebases have been fixed to not use the .data
section, the warning workaround can be disabled.
Change-Id: I675d169a5d2f16e1e9ae05f95e045e9ef3d12208
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: I657d09f05070f5a88a4a162872c961db869a8df3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: I9593c24f764319f66a64715d91175f64edf10608
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The baseboard uses port USB2 #9, and USB3 #1, but vell does not,
therefore set the port configuration to EMPTY.
Change-Id: I0d03b967fd2a051205ad5807f0bd8916bad7c036
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The PMC is accessed via sideband registers, so the PCI device is not
needed.
Disabling it solves a bug where the laptop cannot be powered on
without the charger connected.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I78f4aa4567dfc154ef5cb21f8746265259cd53e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64451
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPTF is not used, so disable the corresponding PCI device.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9e4a3bada13dcabc1af3e1e5b3c215939f8239fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Remove the subsystem device ID for HDA devices, so that the correct
Intel [8086:xxxx] is used. This was an old workaround for Windows
that is no longer required with a new driver.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I63d6a4b0f19d400d683cab5dacca787d6c6a0fdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set S3 assertion time to 28000us as this is sufficient time for
rails to discharge.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4a14e7b30bb1fc4c0c1d3ff2f75069863458487f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64447
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The USB ports use both OC0 and OC1. Whilst they work perfectly with
OC_SKIP, set them to the correct pins.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If173b443d9770083d76519b854b513d8e47b9e71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The OC pin was set to 0, which isn't connected. All USB ports are
connected to OC1.
This solves a strange issue where the Lite can't be powered on without
the charger connected.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I700ddde291f0e4be6e3787e2da13f6d3ece736b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Based on the constraints for CML.
Fixes the following warnings in Linux on system76/oryp8 and
system76/gaze16, which have an NVIDIA GPU on the bridge.
pcieport 0000:00:01.0: can't derive routing for PCI INT A
pcieport 0000:00:01.0: can't derive routing for PCI INT B
This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack trace on every boot and on S3 suspend.
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000fb84c354>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: Ibc968aaa7bf0259879097ff69d2543dcfa2e5e4b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This gives a warning when there's a period at the end of the commit
subject line.
Change-Id: If95bef3ba01e0ac13ce18045928081040abef4fd
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Checkpatch was looking for a 65 character length, but format-patch adds
the text "Subject: [PATCH] " before the actual subject. Checkpatch
needs to account for that when looking at the line length.
Lines 2863 & 2864 have their indentation fixed as well.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f2ee6e0f1b14ae6393ed7e64ba1266aa9debc7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The commit message wasn't being parsed because there's no filename
associated with it in the patch output. This change adds the "filename"
for the commit message in Gerrit for any errors that have a line number
but no filename.
calculations is intentionally misspelled as cacluations as a test.
Change-Id: Ie7a2ef06419c7090c8e44b3b734b1edf966597cc
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
In the last coreboot leadership meeting, the doxygen documentation was
declared to be dead. Remove it.
Doxygen style comments can still be added to files, and we may generate
doxygen based documentation, but it won't be for the entire project, but
instead just for those individual areas where it is being maintained.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8983a20793786a18d2331763660842fea836aa2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
With CBFS verification, cbfstool (CB:41121) needs bootblock to be
present in coreboot.pre in order to locate the metadata hash stored in
it. Therefore we have to ensure that bootblock is added to CBFS before
other CBFS files are added.
To solve the problem, create the 'add_bootblock' function, and call it
in the coreboot.pre recipe. Because bootblock.bin is now a prerequisite
of coreboot.pre, it will get built even if CONFIG_BOOTBLOCK_IN_CBFS=n.
BUG=b:233263447
TEST=emerge-guybrush coreboot
TEST=emerge-corsola coreboot chromeos-bootimage
TEST=cbfstool image-kingler.bin print -v
TEST=Kingler booted successfully
BRANCH=none
Change-Id: I385deb8231e44310ee139c3f69f449e75b92b2be
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the mainboard starlabs/laptop/tgl, since
it is obsolete now.
Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the following mainboards, since it is
obsolete now.
* siemens/chili
* starlabs/laptop/cml
Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the Kconfig option `FSP_HYPERTHREADING` to common Intel Kconfig so
that it can be reused by other SoCs. Since not all SoCs support
hyperthreading, make it conditional on `HAVE_HYPERTHREADING`. SoCs
supporting hyperthreading need to select it so that `FSP_HYPERTHREADING`
is available.
Change-Id: I892d48b488cbf828057f0e9be9edc4352c58bbe7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add support for Alder Lake as a separate parsing profile, copying the
existing 'Cannon' profile and adjusting for differences in reset mapping
and GPIO macro generation.
TEST=Generate GPIO macros for MSI PRO Z690-A
Change-Id: I5871394bcb0636c2c803607ffb129441aa934417
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Moli has USBA port4 but Brask didn't use the port4,
so enable USBA port4 in moli.
BUG=b:232656163
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I5308e3102ea9f0718802596a235c0a5cc42e30bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Add WiFi SAR table for mithrax.
BUG=b:231491014
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I847debd7c817225b5b1777c798a14ef10aee3471
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
On Guybrush, the power and lid switches are managed by the EC
and coreboot and the AP have no control over them within this
context. Remove unused GPIO's to prevent coreboot warnings
about resampling at boot.
BUG=b:233771033
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1c68fce817a2a98ce0e8f1d9771d6c630dd5e88a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The HDMI port was specified as a display port. Update to allow
for testing of 4k streaming.
BUG=b:229771029
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ib4dc8a5c6110630cea768f81e34fd7b0a5a62657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On Skyrim, the power and lid switches are managed by the EC
and coreboot and the AP have no control over them within this
context. Remove unused GPIO's to prevent coreboot warnings
about resampling at boot.
BUG=b:233771163
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie369bb7d430bd0dd1f1c1f41bf543a9b18e34db1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64644
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Guybrush, there wasn't a need for a sleep GPIO table.
Remove the TODO and filler table and function to reduce
unnecessary function calls/overhead. Missed changes
to variant.h in initial commit(already merged)
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idba1a9eeea5ea5f5922281668ec17c4f065a654d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64643
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch skips sending DISCONNECT IPC command to PMC if system resumes
from S3.
coreboot notice DISCONNECT IPC command getting timedout during S3
resume if system has AC connected behind Type-C hub. This impacts
system resume time. Please refer TA# 730910 for more information.
coreboot need not send the DISCONNECT IPC command when system resumes
from S3 state.
TEST=Verified system boots to OS and verfied below tests on Gimble
1. coreboot doesn't send the DISCONNECT during S3 resume
2. After S3 resume, system detects the pen drive with Superspeed
3. After system resumes from S3, hot-plug the pen drive, system detects
the pen drive
3. System sends IPC commands when system boots from S0 or S5.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6ad006ae8677919c7dfeca8eec0af11454a2e89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In order to meet the OEM's acoustic specifications, the pre-wake
randomization time (DPA) is set to 100.
BUG=b:232892200
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I65e3fef581ee06fa049e831f246da1328a08518c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The FSP includes a UPD to set the DPA (Dynamic Periodicity
Alteration) PreWake value, which can be used to set the maximum
pre-wake randomization time in "micro-ticks". This patch adds
support for configuring that value.
BUG=b:228410327
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I08897c590a88aba058cb9e364185ea0794e1e7c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Tiger Lake SoC PCI device list.
BUG=none
TEST=Able to build and boot volteer, google board.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27a2f31aa706c4d76e9f0db202422bc129368959
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Separate and add LPDDR4X MT53E2G32D4NQ-046 WT:C support for burnet/esche
ID#1: MICRON - MT53E2G32D4NQ-046 WT:C
BUG=b:225121354
BRANCH=none
TEST=1. emerge-jacuzzi coreboot
2. power on test ok
Change-Id: If720d7bcf185c5c0149a82125ec068fc75e5b3cd
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64069
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SCP core 2 is enabled for MT8195 camera feature. It requires the same
register access permission as SCP core 1. Therefore, we configure the
same domain ID for both cores.
BRANCH=cherry
BUG=b:193814857
TEST=cherry boot ok
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Change-Id: Idf335593936b12c083c926a252fa99c3b76cda6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64575
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Elyes Haouas