Now that we have functioning display code for all platforms,
we can just get rid of this ugly hack used on non-Chromebook
veyrons.
BUG=none
BRANCH=none
TEST=built for Brain, Rialto, Mickey, Romy
Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5
Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282049
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This uses VOP_MODE_NONE for display init on veyron_rialto and
adds a mainboard_power_on_backlight() stub so that we can finally
get rid of SKIP_DISPLAY_INIT_HACK.
BUG=none
BRANCH=none
TEST=built for veyron_rialto
Change-Id: Ia6b420a962fe266e773c804b8e5c68da35848753
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d
Original-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282048
Reviewed-on: http://review.coreboot.org/10784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux. Calls to PMIC
functions to enable HDMI power are moved here as well.
BUG=none
BRANCH=none
TEST=with follow-up patches, we now get a dev screen on Brain.
Change-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013
Original-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282046
Reviewed-on: http://review.coreboot.org/10778
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This avoids any ambiguity or breakage in case the vop_modes get
shuffled around or changed in some future patch or copy+paste job.
Brain and Rialto need some more work done so their devicetree.cb
files will be updated in follow-up patches.
BUG=none
BRANCH=none
TEST=compiled only (for danger, jerry, mickey, romy, speedy)
Change-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db
Original-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282610
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10776
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
EDP-related hardware modifications for v2:
- BL_EN moved from GPIO7_A3 to GPIO7_A2
- EDP_HPD added to GPIO7_B3
BUG=none
BRANCH=none
TEST=built and booted Danger v2 with EDP panel attached, saw dev
mode screen come up
Change-Id: I47383610082b371a612aced656e56f1bd1cfa098
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b
Original-Reviewed-on: https://chromium-review.googlesource.com/280855
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are all Kconfig symbols that have been removed or renamed.
USE_PRINTK_IN_CAR was removed in commit 8c4f31b3
Drop the USE_PRINTK_IN_CAR option. It's a bogus decision...
DYNAMIC_CBMEM was removed in commit e2b0affd
Remove Kconfig variable that has no effect
MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc
Remove Kconfig variable that has no effect
CACHE_ROM was removed in commit 4337020b
Remove CACHE_ROM.
SMM_MODULES was removed in commit 44cbe10f
smm: Merge configs SMM_MODULES and SMM_TSEG
INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218
soc/fsp_baytrail: Fix use of microcode-related Kconfig variables
CAR_MIGRATION was removed in commit cbf5bdfe
CBMEM: Always select CAR_MIGRATION
REQUIRES_BLOB was removed in commit 70c85eab
build system: Retire REQUIRES_BLOB
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit
66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b
uart: Redefine Kconfig options
CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit
afa7b13b - uart: Redefine Kconfig options
Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10766
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10764
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This fixes the build with CONSOLE_CBMEM_DUMP_TO_UART.
Change-Id: Ibe79239c5799a5c4a08ed195fce4d0c63d629ca4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10769
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch fixes up verified boot (vboot2) configuration of all
tegra 124 bases boards in the tree.
Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10761
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Otherwise the Chrome OS build won't succeed.
Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10760
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Copied from speedy, with changes to mainboard.c (and speedy -> minnie renames
across the directory)
Change-Id: Ib38f0b15da8306984869e7ee7b4ddf366b0df82c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10757
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.
Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.
Change-Id: I8630e86a4b0e8756693f8989ce147d6d762cefe1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Exynos SoC code and vboot really don't get along and things are not even
in a good shape in Chrome OS' top of tree. Disable but don't rip out the
support functions, so it could be revived.
Change-Id: I982c5a3731b527fd1f1579e9de353819da656452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10730
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Initializing timestamps and writing the "start romstage" timestamp already
happens earlier.
One question to sort out is what to do about the migration into cbmem, but at
least this compiles again.
Change-Id: Ie8a0b7998c6c9da71f036857987f3c781385034f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Current vboot wants that function.
Change-Id: I9d3a592c448cf2af10f76cae4518341cbc0a6f41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
A lot changed here between Chrome OS and upstream, and these changes are
needed to reflect that.
Change-Id: I7195861465388d0f6a7cb540ebf4e410e38c260a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10723
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.
Change-Id: Iecfd37e79883d826e15c474d77095fbbbb2b7cea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10705
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.
Change-Id: I59a4f892ca84d475d8f46c8f8c1906dae10ad32d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
vboot configuration (separate stage or not, which stage loads romstage)
depends on SoC properties (eg. amount of SRAM), not on board specifics, so
move this part of the configuration to the SoC.
Change-Id: I70b4cd1794ddf2aba7cdae94859ea1d76ae019f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
romstage requires some button accessor functions for the Chrome OS boot flow.
Change-Id: I3f90d66b103e0610931c183dd5f5679ca6f910f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10697
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch adds the Veyron_Shark mainboard as a clean copy of Veyron_Speedy.
- board-ID differentiation removed, see mainboard.c
- speedy -> shark rename
BRANCH=None
BUG=None
TEST=Compiled.
Change-Id: I3b743a97f152f49647eee87be8f1497377ccacb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac2ca328adf7e0dd879f51bbeae3cc11bceebf86
Original-Change-Id: I8a7cc9acb199ecf23b388c66f6885931ea3ec219
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/276490
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/10699
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Not all devices have a lid switch, so we need to state this
somehow. Since the alternative would be to extend get_lid_switch()'s
semantics to become a tri-state (open, closed, N/A), do this
through Kconfig.
BRANCH=none
BUG=chromium:446945
TEST=none
Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273850
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The function was used locally and in ramstage to set some
coreboot tables. It's also needed in romstage to deal with
"lid closed" behaviour.
BRANCH=none
BUG=chromium:446945
TEST=none
Change-Id: I8ad7061328c45803699321aa9f5edb0ed2288a8d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 78281a104fb9d79696a6ceb2a9a89a391146a424
Original-Change-Id: I56314b9dc9062dd61671982e7ec0ff15d7eb1bae
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273609
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This re-factors SDMMC power on/off to make corrections and take
differences between board versions into account. To avoid similar-
but-different case switch statements in romstage.c and mainboard.c,
power on/off functions for SDMMC are split into their own .c file.
BUG=none
BRANCH=none
TEST=built and booted of micro-SD card on Danger v2
Change-Id: Ib3069c35ceff1ff98b49579a6298681c1390beee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eecfee4a5dd39073b5f966a25991a594b3c4b519
Original-Change-Id: Id86ae7f40687e843ffc4e7769309d4678ad54f49
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280853
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux.
We'll add EDP/HDMI auto-detection in an upcoming patch.
BUG=none
BRANCH=none
TEST=set vop_mode to 1 in Danger's devicetree.cb and saw
dev mode screen output to HDMI display.
Change-Id: I2a208059fee74d436b5a5bedbc677bc59525f935
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 721f326319f727afcf73a0c21d20d26cb463ad71
Original-Change-Id: I139d39749963d4121aaeec0c3da37d825ffa94ac
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280849
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10684
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the System Board Hardware ID to fix the warning:
dsdt.aml 88: Device (MB) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
Change-Id: I063580142ae8053fdc05e165c01e86b8b7cd5ca6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10668
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Where vboot verification can start, and how the code flow looks like is more a
property of the SoC (and its properties, like amount of SRAM) rather than the
board.
Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10662
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
vboot requires it.
Change-Id: Iae2310c9b9c311c3f64b8417295685261ba404b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.
Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10640
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
CAR_MIGRATION was removed in commit:
cbf5bdfe - CBMEM: Always select CAR_MIGRATION
ALT_CBFS_LOAD_PAYLOAD was removed in commit:
cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD
MARK_GRAPHICS_MEM_WRCOMB was removed in commit:
30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB.
EXTERNAL_MRC_BLOB was removed in commit:
0aede118 - Drop unused EXTERNAL_MRC_BLOB
CACHE_ROM is only in Google's codebase.
LID_SWITCH is only in Google's codebase.
DEFAULT_POST_DEVICE_LPC is only in Sage's codebase.
ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used.
HUDSON_NOT_LEGACY_FREE never existed as far as I can tell.
MAINBOARD_DO_EDID never existed as far as I can tell.
Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10616
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The default route does work for all Chromebooks and is replaced
with platform-specific one in follow-up.
Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10442
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This is only needed on boards that still provide old style PIRQ
tables.
Change-Id: Ie299de2937e5b91b7b3e1d1110e40be23c6d9f52
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10508
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Mickey:
- Does not have power key
- Does not have an audio codec(all audio goes thru HDMI)
- VCC18_LCD moved to VLDO8 and needs to be turned on (was
connected to VSWOUT2 earlier)
BUG=none
BRANCH=none
TEST=Boot from mickey board, and hdmi work normal
Change-Id: I88cdc41ce8bb96a6b17aeb7f24b1c5619471b24e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c966edfa29df1049c469442dc3ad8bf8b4197b1
Original-Change-Id: I3d98203185f52ed751a5d3045a0ee8f9b4dfbc71
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274876
Reviewed-on: http://review.coreboot.org/10630
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix by checking the actual function return value (the search
address pointer), rather than the search length value (which isn't
guaranteed to be sane or useful).
Change-Id: I226c635ddbbc916b02494fcd97df27d141cc2c7f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10516
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Commit 899d13d (cbfs: new API and better program loading) broke
panther's lan init when no vpd.bin present from which to read
the MAC address. Fix this by checking the validity of the search
address pointer, rather than the search length.
Change-Id: I8c7ca410d8ce5c5d92242a21c4c2ff4c001a68bd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10509
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Copy the Peppy directory. No changes.
Change-Id: I3fa382eaa40f642df8bc09ab69be67cbe9f3671a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10499
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Taken from CrOS, including everything up to commit da4c33913.
Adapted to upstream.
Change-Id: I095e6726a220200ba17719fc05fcdc521da484e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10432
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change the Kconfig board name symbol to uppercase to match
other symbols and to match the capitalization in the Kconfig
file where it's used in an expression.
Change-Id: I04ccb57cc15a6d7430f8d04136beb8384caa6c04
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10440
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This simply copies veyron_brain to veyron_mickey and makes the
minimal set of changes (s/brain/mickey) to make it compile. The
follow-up patch will take into account board differences.
BUG=none
BRANCH=none
TEST="emerge-veyron_mickey coreboot" doesn't fail
Change-Id: I7d029b36d2fb865446490b896117ade632325a52
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34f6b391290f99caf517d7e98c31c89dc57309be
Original-Change-Id: I03a2b80eb441384f363910467180479521765431
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271360
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10408
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This simply copies veyron_brain to veyron_romy and makes the
minimal set of changes (s/brain/romy) to make it compile. The
follow-up patch will take into account board differences.
BUG=none
BRANCH=none
TEST="emerge-veyron_romy coreboot" doesn't fail
Change-Id: Ice1bc012bddd6c51b43944747e0df3ffa34207fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ab849178b69cf2323f126e503bd61080048240a
Original-Change-Id: I0516ce94fd3c6a38170fae221a070f503ccfaf0f
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271345
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10407
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
A new CBFS API is introduced to allow making CBFS access
easier for providing multiple CBFS sources. That is achieved
by decoupling the cbfs source from a CBFS file. A CBFS
source is described by a descriptor. It contains the necessary
properties for walking a CBFS to locate a file. The CBFS
file is then decoupled from the CBFS descriptor in that it's
no longer needed to access the contents of the file.
All of this is accomplished using the regions infrastructure
by repsenting CBFS sources and files as region_devices. Because
region_devices can be chained together forming subregions this
allows one to decouple a CBFS source from a file. This also allows
one to provide CBFS files that came from other sources for
payload and/or stage loading.
The program loading takes advantage of those very properties
by allowing multiple sources for locating a program. Because of
this we can reduce the overhead of loading programs because
it's all done in the common code paths. Only locating the
program is per source.
Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9134
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Not used anywhere.
Change-Id: I9bab092d285aaebdf9283ba08e23197f9785b3a6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
