Commit Graph

119 Commits

Author SHA1 Message Date
Peter Stuge c39cb144e9 flashrom: Driver for ST M29F002T/NT/B. T/NT TEST_OK_ PROBE READ ERASE WRITE
Test report from Julia. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Julia Longtin <juri@solarnetone.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 06:42:02 +00:00
Peter Stuge c800eeb39b flashrom: SST25VF040B using 0x90 identification and AAI write.
SST AAI is Auto Address Increment writing, a streamed write to the flash chip
where the first write command sets a starting address and following commands
simply append data. Unfortunately not supported by Winbond SPI masters.

From July 2008.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:37:40 +00:00
Peter Stuge 36b3932f99 flashrom: Winbond SuperIO SPI driver.
Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:08:45 +00:00
Peter Stuge 8991302f54 flashrom: Export Winbond SuperIO register access functions in board_enable.c.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 02:34:51 +00:00
Stefan Reinauer 713ee92c96 flashrom: Darwin / Mac OS X
Through DirectIO from coresystems GmbH we now support Darwin/Mac OS X.
DirectIO is available at http://www.coresystems.de/en/directio

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 01:23:31 +00:00
Stefan Reinauer 53ac3947db flashrom: Abstract mmap() in physmap.c and only open /dev/mem on the first physmap() call.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 01:10:48 +00:00
Peter Stuge 8c4421ddbd flashrom: Change flashrom.c:map_flash_registers() from int to void.
The function exit()s on failure, and no callers check the return value.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 00:39:57 +00:00
Stefan Reinauer 09c0b7c61d flashrom: Change FreeBSD #ifdef into #if defined()
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 00:07:25 +00:00
Peter Stuge 2e5481356f flashrom: Check all mmap() calls and print helpful Linux error message.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-23 05:23:06 +00:00
Sven Schnelle d32b9e605f Add SST49LF020 support.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07 12:35:09 +00:00
FENG yu ning a8faa2a479 * add a generic preop-opcode-pair table.
* rename ich_check_opcodes to ich_init_opcodes.

* let ich_init_opcodes do not need to access flashchip structure:
  . move the definition of struct preop_opcode_pair to a better place
  . remove preop_opcode_pairs from 'struct flashchip'
  . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure

* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.

* fix a coding style mistake.

Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-15 02:32:11 +00:00
Carl-Daniel Hailfinger b3b2804482 Add 28 flash chips of the MX29 series to the flashrom ID table and
support the MX29LV040C.

MX29LV040C probe and read support tested by khetzal on IRC.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-10 10:32:05 +00:00
FENG yu ning 8a07f703ec Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI
configuration is locked down.

Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08 18:16:58 +00:00
Carl-Daniel Hailfinger fcf9be3b93 Add RDID/REMS IDs for the following flash chips:
SST_25VF512A_REMS
SST_25VF010_REMS
SST_25VF020_REMS
SST_25VF040_REMS
SST_25VF040B_REMS
SST_25VF080_REMS
SST_25VF080B_REMS
SST_25VF032B_REMS
SST_26VF016
SST_26VF032
W_25X16
W_25X32
W_25X64

Straight from the data sheets.

The REMS IDs help in case the RDID opcode is unavailable (due to opcode
lockdown) or unsupported by the chip.

Some day, we need to pair probe functions together with IDs. Multiple
pairs can exist per chip and duplicating chip definitions does not
really make sense.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 00:58:10 +00:00
Stefan Reinauer d53f3e7546 Replace #ifdefs for sc520 systems by run time probing.
fixes #109

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 21:24:40 +00:00
Carl-Daniel Hailfinger f86f1fe961 If a chip has any TEST_BAD_* flag set, we don't even list the
unsupported functions, giving the user the impression that the
unsupported functions are tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 23:45:27 +00:00
Jason Wang f22ce41840 Add support for the AMD/ATI SB600 southbridge SPI functionality.
This has been tested by Uwe Hermann on an RS690/SB600 board.

Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 21:36:51 +00:00
Carl-Daniel Hailfinger 6f24cbc083 Flashrom already has the following probe functions:
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID

RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.

The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 01:25:00 +00:00
Carl-Daniel Hailfinger 7cb70d9abd Check for failed SPI command execution in flashrom. Although SPI itself
does not have a mechanism to signal command failure, the SPI host may be
unable to send a given command over the wire due to security or hardware
limitations. The current code ignores these mechanisms completely and
simply assumes almost every command succeeds. Complain if SPI command
execution fails.

Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.

Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:41:02 +00:00
Carl-Daniel Hailfinger ef3f7e38ea The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.

Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D

Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642

Add the ID, but no probing function for this chip:
AT25F512A

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-15 13:55:43 +00:00
Carl-Daniel Hailfinger aad6502d8a Add support for 8 new chips to flashrom and fix up 2 existing chips
as well.
Replace age-old TODO comments with real explanations.

Fixed chips:
Fujitsu MBM29F400TC (ID definition)
Macronix MX29F002T (chip name)

New chips:
Fujitsu MBM29F004BC
Fujitsu MBM29F004TC
Fujitsu MBM29F400BC
Macronix MX25L512
Macronix MX25L1005
Macronix MX25L2005
Macronix MX25L6405
Macronix MX29F002B

Straight from the data sheets, compile tested only.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-04 12:11:12 +00:00
Carl-Daniel Hailfinger 6287e2e7aa Add additional SPI sector erase and chip erase command functions to
flashrom. Not all chips support all commands, so allow the implementer
to select the matching function.
Fix a layering violation in ICH SPI code to be less bad. Still not
perfect, but the new code is shorter, more generic and
architecturally
more sound.

TODO (in a separate patch):
- move the generic sector erase code to spi.c
- decide which erase command to use based on info about the chip
- create a generic spi_erase_all_sectors function which calls the
generic sector erase function
  
Thanks to Stefan for reviewing and commenting.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 00:02:11 +00:00
Carl-Daniel Hailfinger 8a9e23c586 Add support for the ST M50FW002 chip to flashrom. Identification only,
erase/write are not implemented.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

tested and
Acked-by: Elia Yehuda <z4ziggy@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 14:25:11 +00:00
Stefan Reinauer a69d1db504 Flashrom support for some Numonyx parts (M25PE)
using block erase d8 as discussed with Peter Stuge

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 22:13:20 +00:00
Uwe Hermann 1aa329dcb0 Coding-style fixes for flashrom, partly indent-aided (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-18 21:14:13 +00:00
Mats Erik Andersson 0994c397a5 Support for AM29F002(N)B[BT]. Fully tested on AM29F002NBT.
Probing, reading, and erasing use the Jedec-routines,
whereas writing resort to the recent write_en29f002a(),
since also these chips use a byte wise algorithm.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-07 12:21:12 +00:00
Mats Erik Andersson ad9bdb4345 Activate proper support for EN29F002(A)(N)[BT].
Fully tested for Probe/Read/Erase/Write on EN29F002NT.
Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()'
are still in use, but a tailored 'write_en29f002a()' is
needed due to a byte wise writing mechanism for this chip.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 13:19:02 +00:00
Peter Stuge ec9e6e33a4 flashrom: Winbond W39V040C and MSI K8T Neo2-F
W39V040C does standard JEDEC commands except chip erase so add a small driver.
probe_w39v040c() prints the block lock pin status when a chip is found.

The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs.

Many thanks to Daniel McLellan for testing all of this on hardware!
Build tested by Uwe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21 17:48:40 +00:00
Peter Stuge a4793182e8 flashrom: Trivial SPI cleanups
While writing a new SPI driver I fixed some things in the SPI code:
All calls to spi_command() had unneccessary #define duplications, and in some
cases the read count define could theoretically become harmful because NULL was
passed for the read buffer. Avoid a crash, should someone change the #defines.

I also noticed that the only caller of spi_page_program() was the it87 driver,
and spi_page_program() could only call back into the it87 driver. Removed the
function for easier-to-follow code and made it8716f_spi_page_program() static.
The ichspi driver's static page functions are already static.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07 06:38:51 +00:00
Carl-Daniel Hailfinger 5bc95858d5 r3415 removed symbolic constants for device IDs by accident.
flash.h is a database of known IDs, whereas flashchips.c is a database
of chips for which support has been implemented. Keep it that way.

Trivial.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06 23:04:01 +00:00
Andreas Thienemann ce17f6bdb0 flashrom: Add AMIC A29002
This patch adds support to the AMIC A29002 chip in its top and bottom
configuration to flashrom. Additionally, the alphabetic order of the
AMIC chips was fixed.

The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>.

A29002T PREW functionality was tested and works.

This flash chip has asymmetric sector layout so it is important to use the
mx29f002 driver, which does chip erase before writing, rather than am29f040b,
which uses sector erase.

Signed-off-by: Andreas Thienemann <andreas@bawue.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06 17:35:30 +00:00
Stefan Reinauer d9b7ae8bec First attempt to clean up SPI probing and create a common
construct: the flash bus.

At some point the flash bus will be part of struct flashchip.

Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.

Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 23:45:22 +00:00
Rudolf Marek d8a7e7d043 Mine AMIC flash chip needs 4 bytes RDID. Following patch adds support for that.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 21:45:17 +00:00
Rudolf Marek 4a17e02003 This patch adds support for VIA SPI controller on VT8237S. It is similar with
few documented exceptions to ICH7 SPI controller.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 21:38:30 +00:00
Stefan Reinauer a1dd9142c6 * ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-27 16:28:34 +00:00
Peter Stuge b05b6a2555 flashrom: Remove dead M-Systems Disk on Chip code
DOC support has been disabled by default for many years. The write function
does nothing but print text. It has a call to write_page_md2802() commented
out, but that function does not exist. This is dead code with ugly #ifdefs.

Updates README to reflect that there was a time when there was code, but it
didn't work. Removes M-Systems #defines and also includes svn rm msys_doc.*

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 17:06:41 +00:00
Jens Kuehnel 42b127fe22 flashrom: Add support for AMIC Technology A49LF040A and do not probe W29EE011 anymore
Jens sent the first patch that added A49LF040A to flash.h and flashchips.c
using _jedec and _49lf040 functions.

An issue was found with probe_w29ee011() for the Winbond W29EE011, which
caused the A49LF040A to no longer respond to any commands.

Ward made a patch to disable probing by default for the W29EE011 following
some discussion. Using -c W29EE011 will make flashrom probe for the chip.

Peter did some more datasheet diving and found that the Pm49FL00x functions
suited this chip quite well because of the block locking registers in
A49LF040A, and finally tested PROBE READ ERASE WRITE to work on ALIX.3c3.

Ward confirmed that this works on alix.2c3 too.

Signed-off-by: Jens Kuehnel <coreboot@jens.kuehnel.org>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18 13:36:34 +00:00
Peter Stuge 646eb245e6 flashrom: Force read unknown flash chips
When flash chip detection fails, it is still useful and possible to read the
flash chip contents. If no flash chip is found in normal probes and the
-f -r -c CHIPNAME options are given, a successful probe for the specified
chip is forced, and then flashrom reads the flash chip using either the read
function for the specified chip, or if there is none, a simple memcpy().

The patch also moves the global variable int force in flashrom.c into main()
and passes it as a parameter to layout.c:show_id(), which was the only other
function that used the variable. This is needed to avoid confusion with the
new parameter int force which is added to flashrom.c:probe_flash() and used
to force probe success for the chip named in char *chip_to_probe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18 02:08:40 +00:00
Peter Stuge bc18fbbc60 flashrom: Add support for Amic Technology A29040B flash chip.
PROBE READ tested by Lyos Gemini Norezel on BioStar P4M80-M4.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-11 02:24:15 +00:00
Mart Raudsepp 41b35b52d8 Revert r3357 and fix it as intended to (forgotten header commit instead of typo)
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 23:51:55 +00:00
Rudolf Marek f40532c2b3 Add support for Amic A25L40P SPI flash.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 13:42:23 +00:00
Andriy Gapon 4b1cde877c Changes to make flashrom compile (and work) on FreeBSD.
This patch addresses different argument order of outX() calls,
FreeBSD-specific headers, difference in certain type names and system
interface names, and also FreeBSD-specific way of gaining IO port
access.

Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 13:22:45 +00:00
Nikolay Petukhov ce1fb9d4e9 flashrom: Support Pm49FL004/2 Block Locking Registers
The PMC chips understand both LPC and FWH flash commands. When in FWH mode
(MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
Locking Registers by default lock the flash chip for write and erase - in
addition to any chipset write protection.

This patch adds unlock operations before Pm49FL004/2 write and erase, and
it includes an svn mv pm49fl004.c pm49fl00x.c

Thanks go to Nikolay for this patch.

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Bari Ari <bari@onelabs.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17 01:08:58 +00:00
Dominik Geyer fac0afb87d Add support for SPI chips on ICH9. This is done by using the generic SPI
interface.

Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 12:55:55 +00:00
Carl-Daniel Hailfinger e3da00de8d Lots of new SST flash chip IDs. Only a subset has been added to
flashchips.c, but the IDs in flash.h will make lookups easier if anybody
wants to add support for them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 03:24:43 +00:00
Carl-Daniel Hailfinger a4868c44b5 Add support for the JEDEC RES (Read Electronic Signature and Resume from
Powerdown) SPI command to flashrom to identify older SPI chips which
can't handle JEDEC RDID. Since RES gives a one-byte identifier which is
shared among many different vendors and even different sizes, we want to
match RES as a last resort if RDID returns 0xff 0xff 0xff.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

This is a heavily reworked version of a patch by Fredrik Tolf, which was
Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 03:19:49 +00:00
Carl-Daniel Hailfinger 3f09561ec4 Add more infrastructure for flashrom ICH9 support.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:51:22 +00:00
Carl-Daniel Hailfinger 68db3a2bdc Check the JEDEC vendor ID for correct parity. Flash chips which can be
detected by JEDEC probe routines all have vendor IDs with correct
parity. Use a parity check as additional hint whether a vendor ID makes
sense.
Note: Device IDs have no parity requirements whatsoever.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:03:06 +00:00
Carl-Daniel Hailfinger 1984067a86 Add lots of ATMEL SPI flash chips to flash.h.
Add a few flashchips already mentioned in flash.h to flashchips.c

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 04:27:02 +00:00
Carl-Daniel Hailfinger b77fb6bd52 flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
file it87spi.c.
No behavioural changes, but greatly improved SPI abstraction.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 23:03:12 +00:00