Xavi Drudis Ferran 1d80e51017 Prepare for next patches (Improving BKDG implementation of P-states, ... CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj], Northbridge/core synchronization FIFO pointer adjust, to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2011-02-27 23:50:30 +00:00
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arch/x86	This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code.	2011-02-14 18:47:37 +00:00
boot	Rename build system variables to be more intuitive, and	2010-09-30 16:55:02 +00:00
console	rename CONFIG_SERIAL_POST to CONFIG_CONSOLE_POST	2011-01-28 07:47:35 +00:00
cpu	Prepare for next patches (Improving BKDG implementation of P-states,	2011-02-27 23:50:30 +00:00
devices	Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functions	2011-02-03 09:14:40 +00:00
drivers	All the values should stay untouched or be set automatically by the resource	2010-12-26 16:49:57 +00:00
ec	pmh7.[ch]: Add missing license headers.	2011-02-02 23:56:15 +00:00
include	Extended K8T890 driver to include the K8T800 and K8M800 northbridges	2011-02-16 13:43:00 +00:00
lib	This patch gets usbdebug console working in romstage.	2011-01-28 08:05:54 +00:00
mainboard	Make AMD Fam10h CPU microcode updates optional in Expert mode	2011-02-26 23:29:44 +00:00
northbridge	Add 300 MHz and 500 MHz HT frequency limits	2011-02-27 02:48:41 +00:00
pc80	Build failure because of src/pc80/mc146818rtc_early.c unused variable	2011-01-31 21:03:14 +00:00
southbridge	It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.	2011-02-26 13:34:01 +00:00
superio	It turns out that the code which enables specific LDN is somewhat buggy.	2011-02-19 14:51:31 +00:00
vendorcode	Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.	2011-02-14 18:30:54 +00:00
Kconfig	Add new ec subdir for Embedded Controllers and common ACPI EC support	2011-01-27 11:43:03 +00:00
Kconfig.deprecated_options	move single options out of main menu and remove stray "options"	2011-01-05 02:27:53 +00:00