466ca2c1ad
This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning. Minimal scanning is a frequently requested feature. To enable it, we add two new variables to src/Kconfig CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage. MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning. Some devices must be scanned in all cases, such as 0:0.0. To indicate which devices we must scan, we add a new mandatory keyword to sconfig It is used in place of on, off, or hidden, and indicates a device is enabled and mandatory. Mandatory devices are always scanned. When MINIMAL_PCI_SCANNING is enabled, ONLY mandatory devices are scanned. We further add support in src/device/pci_device.c to manage both MINIMAL_PCI_SCANNING and mandatory devices. Finally, to show how this works in practice, we add mandatory keywords to 3 devices on the qemu-q35. TEST= 1. This is tested and working on the qemu-q35 target. 2. On CML-Hatch Before CL: Total Boot time: ~685ms After CL: Total Boot time: ~615ms Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> |
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.. | ||
dram | ||
azalia.h | ||
azalia_device.h | ||
cardbus.h | ||
device.h | ||
drm_dp_helper.h | ||
hypertransport.h | ||
hypertransport_def.h | ||
i2c.h | ||
i2c_bus.h | ||
i2c_simple.h | ||
mmio.h | ||
path.h | ||
pci.h | ||
pci_def.h | ||
pci_ehci.h | ||
pci_ids.h | ||
pci_mmio_cfg.h | ||
pci_ops.h | ||
pci_rom.h | ||
pci_type.h | ||
pciexp.h | ||
pcix.h | ||
pnp.h | ||
pnp_def.h | ||
pnp_ops.h | ||
pnp_type.h | ||
resource.h | ||
smbus.h | ||
smbus_def.h | ||
smbus_host.h | ||
spi.h |