Bernardo Perez Priego 421ce56f83 soc/intel/alderlake: Add USB TCSS enablement ... In order to detect USB Type C device port as Super Speed, we need to set corresponding bit in UPD UsbTcPortEn. This patch will use device path to determine which port should be enabled. BUG=b:184324979 Test=Boot board, USB Type C must be functional and operate at Super Speed. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I7da63f21d51889a888699540f780cb26b480c26d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-07-02 07:47:50 +00:00
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acpi	soc/intel/alderlake: Enable support for common IRQ block	2021-06-29 21:54:00 +00:00
bootblock	soc/intel/alderlake: Add GFx Device ID 0x46b3	2021-06-21 05:38:58 +00:00
include/soc	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
romstage	soc/intel/alderlake: Update mainboard_memory_init_params() argument	2021-06-24 07:55:12 +00:00
spd	soc/intel/alderlake: Add new memory parts for ADL boards	2021-06-03 15:51:17 +00:00
acpi.c	soc/intel: Drop casts around soc_read_pmc_base()	2021-06-28 04:16:48 +00:00
chip.c	soc/intel/alderlake: Enable support for common IRQ block	2021-06-29 21:54:00 +00:00
chip.h	soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx	2021-06-16 03:50:20 +00:00
chipset.cb	soc/intel/adl: Add SKU specific power limits support	2021-06-07 19:02:02 +00:00
cpu.c
crashlog.c
dptf.c
elog.c
espi.c
finalize.c
fsp_params.c	soc/intel/alderlake: Add USB TCSS enablement	2021-07-02 07:47:50 +00:00
gpio.c	soc/intel/alderlake: Add known GPIO virtual wire information	2021-05-14 08:58:07 +00:00
gspi.c
i2c.c
Kconfig	soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION config	2021-07-01 09:38:31 +00:00
lockdown.c
Makefile.inc	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
me.c
meminit.c	soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards	2021-05-16 22:17:52 +00:00
p2sb.c
pcie_rp.c
pmc.c	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
pmutil.c
reset.c
smihandler.c
soundwire.c	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
spi.c
systemagent.c	soc/intel/adl: Add SKU specific power limits support	2021-06-07 19:02:02 +00:00
uart.c
xhci.c	soc/intel/alderlake: Correct TCSS XHCI Port status offset	2021-06-08 15:25:29 +00:00