Duncan Laurie f5116952bb soc/intel/skylake: Limit xDCI feature when VBOOT is enabled ... Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-03-28 22:52:38 +00:00
..
acpi	mb/google/fizz: update DPTF settings	2018-01-12 18:19:00 +00:00
acpi_tables.c
board_info.txt
bootblock.c
chromeos.c	mb/google/fizz: Set lid status as open	2017-04-24 19:32:24 +02:00
chromeos.fmd	mainboard/google/fizz: Enable separate MRC cache for recovery mode	2017-11-20 23:33:00 +00:00
devicetree.cb	soc/intel/skylake: Limit xDCI feature when VBOOT is enabled	2018-03-28 22:52:38 +00:00
dsdt.asl
ec.c	ec/google/chromeec: Add library function google_chromeec_events_init	2017-10-08 19:38:28 +00:00
ec.h	mainboard/google/fizz: Enable cros_ec_keyb device	2017-09-26 18:44:16 +00:00
gpio.h	mb/google/fizz: Set SATA GPIOs in bootblock	2018-02-11 00:00:07 +00:00
Kconfig	google/fizz: Enable ec sw sync gbb by default	2017-12-21 23:49:47 +00:00
Kconfig.name
mainboard.c	mb/google/fizz: Determine PsysPl3 and Pl4 values	2018-02-06 03:01:01 +00:00
Makefile.inc	mb/google/*: Use newly added Chrome EC boardid function	2017-09-26 15:20:39 +00:00
ramstage.c	mainboard/google/fizz: Check HDMI HPD and DisplayPort HPD	2018-03-06 08:50:51 +00:00
romstage.c	google/fizz: correct memory rcomp settings	2017-11-27 03:55:42 +00:00
smihandler.c