Naresh G Solanki ff48b3b1ec soc/intel/skylake: Enable SMBus based on mainboard config ... Enable SMBus controller based on config in mainboard devicetree.cb BUG=None TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run lspci in OS) based on board devicetree.cb config 'SmbusEnable'. Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>		2017-07-18 22:10:19 +00:00
..
acpi	Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"	2017-07-12 04:00:18 +00:00
bootblock	soc/intel/skylake: Fix PMC address range setup for PCH-H	2017-07-11 11:35:10 +00:00
include	soc/intel/skylake: remove top_of_32bit_ram() declaration	2017-07-17 14:59:56 +00:00
nhlt	intel/skylake: nhlt: Add 48Khz 2ch 16bit config for max98927	2017-05-04 01:57:36 +02:00
romstage	soc/intel/skylake: Enable SMBus based on mainboard config	2017-07-18 22:10:19 +00:00
acpi.c	soc/intel/skylake: Use CPU common library code	2017-06-09 19:24:58 +02:00
chip.c	src: change coreboot to lowercase	2017-06-07 12:09:15 +02:00
chip.h	soc/intel/skylake: Set PsysPL2 MSR	2017-07-14 22:47:25 +00:00
chip_fsp20.c	soc/intel/skylake: Add option to enable/disable EIST	2017-05-16 17:45:38 +02:00
cpu.c	soc/intel/skylake: Set PsysPL2 MSR	2017-07-14 22:47:25 +00:00
dsp.c	skylake: Add Audio DSP device	2016-05-31 18:45:15 +02:00
elog.c	soc/intel/skylake: Remove Heci2 and Heci3 from wake resource list	2017-07-18 19:07:52 +00:00
finalize.c	soc/intel/skylake: Clean up code by using common FAST_SPI module	2017-05-02 18:26:07 +02:00
gpio.c	soc/intel/skylake: Use common PCR module	2017-04-10 20:04:01 +02:00
gspi.c	lib: provide clearer devicetree semantics	2017-04-25 18:14:38 +02:00
i2c.c	intel/common/block/i2c: Add common block for I2C and use the same in SoCs	2017-05-18 06:07:15 +02:00
igd.c	soc/intel/skylake: Use PCI IDs from device/pci_ids.h	2017-06-06 19:42:17 +02:00
irq.c	soc/pci_devs.h: Use consistent naming in soc/pci_devs.h	2017-03-28 16:39:28 +02:00
Kconfig	sgx: Move SGX code to intel/common/block	2017-07-10 17:16:26 +00:00
lpc.c	soc/intel/skylake: Use PCI IDs from device/pci_ids.h	2017-06-06 19:42:17 +02:00
Makefile.inc	sgx: Move SGX code to intel/common/block	2017-07-10 17:16:26 +00:00
me.c	Rename __attribute__((packed)) --> __packed	2017-07-13 19:45:59 +00:00
memmap.c	soc/intel/skylake: remove top_of_32bit_ram() declaration	2017-07-17 14:59:56 +00:00
opregion.c	soc/intel/common/opregion: Use enum cb_err as return value	2017-06-27 17:18:03 +00:00
pch.c	soc/intel/skylake: Clean up code by using common FAST_SPI module	2017-05-02 18:26:07 +02:00
pei_data.c
pmc.c	soc/intel/skylake: Split AC/DC settings for Deep Sx config	2017-04-13 09:09:16 +02:00
pmutil.c	lib: provide clearer devicetree semantics	2017-04-25 18:14:38 +02:00
reset.c	Consolidate reset API, add generic reset_prepare mechanism	2017-06-13 20:53:09 +02:00
sd.c	soc/intel/skylake: Use SCS common code	2017-06-16 17:37:13 +02:00
smi.c	soc/intel/skylake: remove unused SMI functions	2017-05-08 06:10:25 +02:00
smihandler.c	soc/intel/skylake: Clean up code by using common FAST_SPI module	2017-05-02 18:26:07 +02:00
smmrelocate.c	soc/intel/skylake: Wrap lines at 80 columns	2017-03-17 02:34:52 +01:00
spi.c	soc/intel/common: Provide common block fast_spi_flash_ctrlr	2017-05-05 23:40:51 +02:00
systemagent.c	soc/intel/skylake: Use common systemagent code	2017-06-09 17:06:26 +02:00
uart.c	soc/intel/skylake: Use common/blocks/uart code	2017-05-09 17:59:07 +02:00
uart_debug.c	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
vr_config.c	intel/skylake: Support for setting AC/DC loadline	2017-03-15 19:45:55 +01:00