ipq/arm: Redesign hooks for bootblock
The following patches had to be squashed
to properly build all the different ARM boards.
ipq8064: storm: re-arrange bootblock initialization
The recent addition of the storm bootblock initialization broke
compilation of Exynos platforms. The SOC specific code needs to be
kept in the respective source files, not in the common CPU code.
As of now coreboot does not provide a separate SOC initialization API.
In general it makes sense to invoke SOC initialization from the board
initialization code, as the board knows what SOC it is running on.
Presently all what's need initialization on 8064 is the timer. This
patch adds the SOC initialization framework for 8064 and moves there
the related code.
BUG=chrome-os-partner:27784
TEST=manual
. nyan_big, peach_pit, and storm targets build fine now.
Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197835
(cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
arm: Redesign mainboard and SoC hooks for bootblock
This patch makes some slight changes to the way bootblock_cpu_init() and
bootblock_mainboard_init() are used on ARM. Experience has shown that
nearly every board needs either one or both of these hooks, so having
explicit Kconfigs for them has become unwieldy. Instead, this patch
implements them as a weak symbol that can be overridden by mainboard/SoC
code, as the more recent arm64_soc_init() is also doing.
Since the whole concept of a single "CPU" on ARM systems has kinda died
out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had
already been done on Storm/ipq806x, which is now adjusted to directly
use the generic hook.) Also add a proper license header to
bootblock_common.h that was somehow missing.
Leaving non-ARM32 architectures out for now, since they are still using
the really old and weird x86 model of directly including a file. These
architectures should also eventually be aligned with the cleaner ARM32
model as they mature.
BRANCH=None
BUG=chrome-os-partner:32123
TEST=Booted on Pinky. Compiled for Storm and confirmed in the
disassembly that bootblock_soc_init() is still compiled in and called
right before the (now no-op) bootblock_mainboard_init().
Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231940
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57
Reviewed-on: http://review.coreboot.org/7879
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-23 20:09:44 +02:00
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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2015-04-27 23:03:57 +02:00
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ifeq ($(CONFIG_SOC_QC_IPQ806X),y)
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2014-04-10 04:23:54 +02:00
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bootblock-y += clock.c
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2014-04-11 05:35:05 +02:00
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bootblock-y += gpio.c
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2014-05-02 04:37:18 +02:00
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bootblock-$(CONFIG_SPI_FLASH) += spi.c
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2014-12-30 00:52:59 +01:00
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bootblock-y += timer.c
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2018-11-11 01:42:17 +01:00
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bootblock-y += uart.c
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2014-03-19 22:29:48 +01:00
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2014-12-11 05:11:30 +01:00
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verstage-y += clock.c
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verstage-y += gpio.c
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Remove libverstage as separate library and source file class
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are
linked directly into the bootblock or the romstage. However, they're
still compiled with a separate "libverstage" source file class, linked
into an intermediate library and then linked into the final destination
stage.
There is no obvious benefit to doing it this way and it's unclear why it
was chosen in the first place... there are, however, obvious
disadvantages: it can result in code that is used by both libverstage
and the host stage to occur twice in the output binary. It also means
that libverstage files have their separate compiler flags that are not
necessarily aligned with the host stage, which can lead to weird effects
like <rules.h> macros not being set the way you would expect. In fact,
VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86
because their libverstage code that gets compiled into the romstage sets
ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to
run pre-migration.
This patch resolves these problems by removing the separate library.
There is no more difference between the 'verstage' and 'libverstage'
classes, and the source files added to them are just treated the same
way a bootblock or romstage source files in configurations where the
verstage is linked into either of these respective stages (allowing for
the normal object code deduplication and causing those files to be
compiled with the same flags as the host stage's files).
Tested this whole series by booting a Kevin, an Elm (both with and
without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode.
Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18302
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-20 23:32:15 +01:00
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verstage-y += gsbi.c
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verstage-y += i2c.c
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verstage-y += qup.c
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verstage-y += spi.c
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2014-12-11 05:11:30 +01:00
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verstage-y += timer.c
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2018-11-11 01:42:17 +01:00
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verstage-y += uart.c
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2014-12-11 05:11:30 +01:00
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2014-04-10 04:23:54 +02:00
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romstage-y += clock.c
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2014-12-11 05:42:58 +01:00
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romstage-y += blobs_init.c
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2014-04-11 05:35:05 +02:00
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romstage-y += gpio.c
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2014-05-02 04:37:18 +02:00
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romstage-$(CONFIG_SPI_FLASH) += spi.c
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2014-12-30 00:52:59 +01:00
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romstage-y += timer.c
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2018-11-11 01:42:17 +01:00
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romstage-y += uart.c
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2014-05-01 23:45:56 +02:00
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romstage-y += cbmem.c
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2018-02-14 16:47:12 +01:00
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romstage-y += i2c.c
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romstage-y += gsbi.c
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romstage-y += qup.c
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2014-03-19 22:29:48 +01:00
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2014-09-23 02:49:56 +02:00
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ramstage-y += blobs_init.c
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2014-05-01 23:45:56 +02:00
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ramstage-y += cbmem.c
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2014-04-10 04:23:54 +02:00
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ramstage-y += clock.c
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2014-04-11 05:35:05 +02:00
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ramstage-y += gpio.c
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2015-02-12 00:13:04 +01:00
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ramstage-y += lcc.c
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2014-05-14 02:47:57 +02:00
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ramstage-y += soc.c
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2014-05-02 04:37:18 +02:00
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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2014-04-10 04:23:04 +02:00
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ramstage-y += timer.c
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2015-01-13 22:07:48 +01:00
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ramstage-y += uart.c # Want the UART always ready for the kernels' earlyprintk
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2014-05-31 03:01:44 +02:00
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ramstage-y += usb.c
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2014-09-23 02:49:56 +02:00
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ramstage-y += tz_wrapper.S
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2016-07-26 01:57:46 +02:00
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ramstage-y += gsbi.c
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ramstage-y += i2c.c
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ramstage-y += qup.c
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ramstage-y += spi.c
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2014-04-08 00:26:39 +02:00
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2014-04-08 03:59:53 +02:00
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ifeq ($(CONFIG_USE_BLOBS),y)
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2014-04-08 00:26:39 +02:00
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2014-04-08 03:59:53 +02:00
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# Add MBN header to allow SBL3 to start coreboot bootblock
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2015-09-18 00:02:53 +02:00
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$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin
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2014-04-08 00:26:39 +02:00
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@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
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New mechanism to define SRAM/memory map with automatic bounds checking
This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.
The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).
BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.
Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-08-21 00:29:56 +02:00
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./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
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2014-04-08 00:26:39 +02:00
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@mv $@.tmp $@
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2014-04-08 03:59:53 +02:00
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# Create a complete bootblock which will start up the system
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2014-04-15 23:42:30 +02:00
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$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \
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2014-04-08 03:59:53 +02:00
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$(objcbfs)/bootblock.mbn
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2014-12-01 01:10:46 +01:00
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@printf " MBNCAT $(subst $(obj)/,,$(@))\n"
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@util/ipqheader/mbncat.py -o $@.tmp $^
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2014-04-08 03:59:53 +02:00
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@mv $@.tmp $@
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2014-04-08 00:26:39 +02:00
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endif
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2014-04-11 05:53:32 +02:00
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2014-04-11 05:35:05 +02:00
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CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include
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2014-12-07 03:24:56 +01:00
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# List of binary blobs coreboot needs in CBFS to be able to boot up this SOC
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mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn
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# Location of the binary blobs
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2015-05-05 22:27:25 +02:00
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mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq806x
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2014-12-07 03:24:56 +01:00
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# Create make variables to aid cbfs-files-handler in processing the blobs (add
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# them all as raw binaries at the root level).
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$(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\
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$(eval $(f)-file := $(mbn-root)/$(f))\
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$(eval $(f)-type := raw))
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2015-04-27 23:03:57 +02:00
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endif
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