Configure SATA FSP UPD according to mainboard design.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates system agent related registers bit definitions
as per EDS.
For example:
As per CNL/ICL EDS MCHBAR register base is between bit 16-38
but coreboot programming was not aligned with EDS previously.
CNL EDS doc number: 566216
Also provide provision to program 64bit values as per SA EDS definitions
TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value.
Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1. Add a TEMP_SENSOR3
2. Update DFPS (fan performance state) table with values received
from thermal team
3. Update PL1 override to 15W
4. Update PL2 override to 51W
BRANCH=hatch
BUG=b:147792204
TEST=build and verify by thermal team
Change-Id: I21c17c09a097c963f4dd1b7d5f8212c83a639dc3
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 2843aa62:
2019-12-12 Julius Werner 2lib: Move firmware body size reporting to
separate function
to commit id f5367d59:
2020-01-20 Joel Kitching vboot: translate recovery reason info from
vboot 2->1
This brings in 27 new commits.
Change-Id: I7d33337881fa2d36d6e562b0a390b56227cfad55
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
This CL allows MKBP events from the EC to wake the system from suspend
states.
BUG=b:144122000
BRANCH=firmware-hatch-12672.B
TEST=Verify that MKBP events generated from EC will wake the system
from S0ix.
Change-Id: I8a0d2c7ed89fa1ea937a08c3082cc5d3e782efff
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Values as per "IT8772E Preliminary Specification V0.4 (For F Version)".
Some values are unclear on this document, but is the only one I have.
Change-Id: I6d74984f453c47d6ec71963a7dcab961a22a5964
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The firmware configuration (fw_config) field is store in the CBI EEPROM
and it should be used to make firmware customization instead of
sku/variant id.
BUG=b:145519081
TEST=builds
Change-Id: I790998a29e724ecdff8876cca072267537b7cea6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy ec_commands.h directly from Chromium OS EC repo at sha e57217a250.
This is needed for the FW_CONFIG CBI field definition.
Change-Id: Id010721033ebe32ac9c9482d666cf790442a26ee
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups from coreboot so that they are mapped properly.
GPIO communities should be properly configured in GPIO_CFG and
MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured
in GPIO_CFG register while the PMC_GPP_* in pmc.h are used to
configure the MISCCFG registers.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. Verified that after
setting the gpe from devicetree the GPP_EN register for
that community gets updated setting that specific bit.
From the iotools i checked that GPE_EN register for that
community is updated with that specific bit set to 1.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Add Elkhartlake CPU, SA and PCH IDs.
EHL PCH is code named as MCC.
Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update interrupt header and interrupt mapping per Intel Silcon reference code.
Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec.
Reference
PCH BIOS spec#613495
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg
/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The monolith board doesn't support the S3 and S4 states because of the
watchdog and failover mechanisms.
Remove S3 and S4 from the available sleepstates.
BUG=N/A
TEST=build
Change-Id: I01f67d8bb3f9e45caef748caca91eeb6859d7393
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Some boards don't support S3 or S4. The S4 state can't be removed from
the available sleep states.
Add a config item that allows removal of the S4 state from the list of
available sleep states. The S4 state can be removed by selecting the
item on board level.
For the AMD chipsets the SSFG mask is updated to remove the S4 state.
BUG=N/A
TEST=build
Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to VRTT report, add ac/dc loadline configuations in puff device
tree.
BUG=b:147206535
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to puff and checked the log.
All ac/dc loadline configs were set correctly.
Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Use information provided by AGESA to fill the SMBIOS memory tables.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I45bb2fc36cf0c01670e9fc8559d3a6183ea271f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Following the example of change CB:37737 (ee8f969).
Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c'.
Tested-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Change-Id: I2e710ac61843c09a055523c7971e4c05bae56a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix devicetree to advertise the correct USB names and types
in the generated ASL.
BUG=b:146437991
BRANCH=none
TEST=booted and inspected the reported generated ASL.
Change-Id: I133b4db444f9a5f0a36d8e976ae490f24cf307d8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add SMMSTORE support for saving EFI NVRAM variables in
conjuction with Tianocore payload.
Test: none, as this duplicates tested functionality in
amd/stoneyridge.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id05b33edf949611c3f9eac94e7b63a4266c6c4d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The existing rule created a potential race condition between creating
the directory and putting files in there, so use our existing
infrastructure for directory creation instead.
Change-Id: If52a9f558c7d9ce85f71ba53232594699c9d357a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37798
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only the ACPI code needs to be extended, as smihandler.c already
supported it. The _Q50 Method is just _Q18 with changed name.
On Linux, pressing the undock button does nothing, so the only safe
way to undock is to press Fn+F9. With this patch, when the undock
button is pressed, the green LED lights up, and undocking is safe.
Change-Id: Iaaecad031bb1f39dd1a778d0c8eaea6bce9e0f57
Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38446
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Nuvoton NCT5104D GPIO IO VLDN and define an IO base address
unused by any peripheral for GPIO use.
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I034c5d0169b8d97eac97a20c92c22816fd674f79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Now, Super I/O GPIOs can also be controlled directly through
access to I/O registers. VLDN 108 and specific I/O port from a range
<100h; ff8h> may be enabled in mainboard devicetree.
Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35849
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.
Remove the PWRB device from ASL.
BUG=N/A
TEST=tested using fwts on a facebook monolith.
Found-by: fwts 19.12.00
Change-Id: I25a842539ee2e8febc8a1ae88843a71ccb4ee68e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38133
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.
Remove the PWRB device from ASL.
BUG=N/A
TEST=build
Found-by: fwts 19.12.00
Change-Id: I4fac1411fd99475551bc970818759649f80b3f0e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38134
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When regions are resized they are always aligned to the top of the
region. For the BIOS region this is correct. The other regions however
should be aligned to the bottom of the region.
Update the region handling to only align BIOS region to top of region.
BUG=N/A
TEST=verified image resize
Change-Id: Ied0e763b5335f5f124fc00de38e5db1a4d0f6785
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
NOTE: The ME interface was disabled on folio_9470m and revolve_810_g1.
It is assumed that they were ported while the ME was in an abnormal
state (usually due to me_cleaner usage), and that it should be enabled.
In any case, the MEI device is hidden if the ME fails to boot already.
Change-Id: Ibf32a034653946f49f72a2c19c41a4033964ef83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Update Makefile.inc so as to add the SPD data when needed. Tested
building other variants, no spd.bin gets added because they don't select
GENERIC_SPD_BIN.
Tested with BUILD_TIMELESS=1, binary does not change.
Change-Id: I0cda3f839baa227ce6a4b8f0510934125e5afb59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since this board does not have integrated graphics, do not install the
INT15 handler if it is not selected in Kconfig.
NOTE: Since cmos options are not very flexible, this board ends up with
a spurious gfx_uma_size option. Other than that, everything is the same.
Tested with BUILD_TIMELESS=1, binary does not change when ignoring the
cmos options.
Change-Id: I2ebcfd5160773bf98a3d23e797a89e290063d112
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Get ready to squash all the HP Sandy Bridge and Ivy Bridge laptops
together, so as to factor out lots of repeated code.
Tested with BUILD_TIMELESS=1, binary does not change.
Change-Id: I0b68e524b57e3705e91e3cd98be5571b3554bd67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change stapm percentage to 80 and time to 2000 seconds make
DUT meets Lenovo spec and pass CTS respectively.
BUG=b:147333429
TEST=build firmware and install it to DUT and run CTS relevant
test, check temperature whether meets spec.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6a2f059fbd5c89f897cfb46d1f7a82b0923edb17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38443
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These predate hyperthreading so they are not SMP capable unless installed
in a SMP board. Turning SMP off shaves 128 compressed bytes from
ramstage.
Change-Id: I114bdc83ed40ccd9d3996aabf77422236d9d12fa
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Disable Windows driver DPST function
- Set POST resolution to 1800x1200
- Set POST brightness to 225 (0-255 scale)
Test: Boot Windows on EVE, verify display backlight control
functional and no lock ups from switching in/out of tablet mode.
Change-Id: Ida64a44df2449f1ff0dc5c8d0ec7b40a183566a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Base on SATA SI report to fine tune the strength for port 1.
BRANCH=none
BUG=b:147351936
TEST=build and test SATA port works fine.
Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Wonkyu Kim