Commit Graph

5799 Commits

Author SHA1 Message Date
Stefan Reinauer 03f82bd787 Use ACPI text fields consistently with all other boards
LXBIOS and LXB-DSDT are not used in other parts of the tree.
Make names consistent across the tree.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43
Reviewed-on: http://review.coreboot.org/224
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-21 00:31:45 +02:00
Marc Jones 8487229b91 Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.
Change-Id: Ic960fe09fbed2c8a31c7c9ac2c54f6c88efebed3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/219
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Tested-by: build bot (Jenkins)
2011-09-17 20:28:19 +02:00
Marc Jones 96be74c7f6 Enable SATA AHCI for faster boot with SeaBIOS.
Change-Id: Ibd87422680350c112eabe1bb73b237031c3e9d6b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/220
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
2011-09-17 01:53:41 +02:00
efdesign98 d7a696d0f2 Persimmon updates for AMD F14 rev C0
These are the changes for the AMD Persimmon mainboard
required to support the update of the AMD Family 14
cpu to rev C0.  There are many warning fixes; the agesa-
wrapper.c file has been changed to fix the amdinitlate
and amdlaterunaptask routines, and more.

Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/137
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-16 01:51:00 +02:00
efdesign98 83d59b945c Build warning fix for AMD Family 12
This trivial change adds a prototype to an existing
header file to fix a build warning for the AMD family
12 cpus.

Change-Id: Ic666bfbef867d17607eaa0f59570aea987a31f93
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/218
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 19:55:35 +02:00
efdesign98 d91c9b7e3c AMD Inagua platform updates
These changes update the Inagua platform.  The changes
include modifying the Kconfig to suggest video bios
and ahci rom implementations, changing the dimm spd
code to use the correct bus addresses, cleaning up the
makefile a bit, and fixing a duplicate definition
warning associated with the BIOS_SIZE value.

Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/136
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 19:23:56 +02:00
efdesign98 2c66060169 AMD Torpedo platform updates
This update fixes warnings and supports as necessary
the Agesa infrastructure changes required to support
the AMD Family 14 cpu update to rev C0.

Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/138
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 17:30:07 +02:00
efdesign98 4d2d5d5b3e AMD Agesa macro expansion fix
This change fixes the use of a macro that was
previously modified to fix a warning.  The macro
was used in a manner that doubly incremented a
pointer.  The pointer increment was removed from
the macro call and moved elsewhere.  In addition,
an unused macro was removed from both Family 12
and Family 14 code.

Change-Id: I577794bbc55d18f21170dda1d0bbdc6d776ce392
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-15 09:56:08 +02:00
efdesign98 3c59158810 AMD SB800 early console use fix
This change removes printk's that occur before
console init is called.  In the best case, these
would cause an extremely slow boot, and in the
worst case would cause a complete post failure.

Change-Id: I50388e71225e95db602aa45835c39126c1c920a3
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/216
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 00:44:09 +02:00
efdesign98 0bcfff7908 AMD Agesa changes to fix F14 boot issues
This collection of changes fixes a buffer addressing
issue by removing one level of indirection, fixes an
Agesa HT mailbox retrieval bug, and fixes a buffer
location-by-signature issue.

Change-Id: Ic8a8cb3f9abddd9ad59343a85dbbee5aa7633be3
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/215
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2011-09-15 00:24:00 +02:00
efdesign98 3f5ebd6533 AMD F14 Northbridge updates
This change is warning and whitespace fixes in the
northbridge code for AMD Family 14 rev C0 cpu update.
This does not address warnings in the mainboard,
Agesa, Cimx, or southbridge code.

Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/134
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 23:45:40 +02:00
efdesign98 99b6674bd2 Update to Asrock E350m1 for AMD F14 C0
This updates the E350m1 Agesa wrapper code to fix an
issue with AmdLateRunApTask.  It now passes the function
parameter through to the Agesa routine.  There is also
a change to the platform_cfg.h file that makes the
definition of BIOS_SIZE dependent on whether or not
it was defined earlier.

Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/139
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 22:59:14 +02:00
Kerry She 7b7b2c9ef9 mainboard: add avalue/eax-785 ITX mainboard
It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i.
Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie
slot, Lan, audio, PS2 keyboard/mouse and USB are verified.

Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/208
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 19:49:48 +02:00
Kerry Sheh 8c69b1d13b rs780: hide unused gfx ports and gpp ports
Hide the unused gfx ports and gpp ports if they are not configured as hotplug.
lspci -vvv will get more accurate information under Linux,
tested on avalue/eax-785e.

Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-14 07:47:30 +02:00
Patrick Georgi a25828dd0e Provide mechanism to local additions to the build
site-local/ is an optional directory for local additions to the build.
If site-local/Makefile.inc exists it will be parsed and used.

Use it to define VGA option roms, splash screens, extra rules to the
tree...

Change-Id: I0c6ee43ffa40e6c3f193db081ab551ab75bc7478
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/212
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:44:25 +02:00
Mathias Krause 14b67f716d superiotool: Don't compile with -Werror
Older libpci version have headers using 'long long' which isn't allowed
in ANSI C. Since we cannot control the libpci version installed in the
system nor in generall have complete control over system headers, simply
skip using -Werror in our makefile.

Change-Id: Ibc1e57bef033bf4971f4108d078222dcf168d5e3
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/210
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:43:33 +02:00
Mathias Krause 9beb5df3c4 inteltool: fixed 64 bit build
The inline assembly for cpuid() was 32 bit specific. Additionally a
format string referencing a size_t argument wasn't using the %z length
modifier.

Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/211
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:43:19 +02:00
Mathias Krause 5782fee0e1 inteltool: Fixed building of position independent executables
When building a position independent executable (PIE) EBX is used
internally by the compiler to generate position independent address
references so it cannot be used in the clobber list. Use the already
existing code for the Darwin plattform for that case, too -- it'll
preserve the EBX value.

Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/209
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:43:04 +02:00
Patrick Georgi c230058199 libpayload: Add get_option_from()
This function allows reading the nvram configuration table from
locations other than the cbtable.

Change-Id: I56c9973a9ea45ad7bf0185b70d11c9ce5d0e0e1b
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/213
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 07:42:20 +02:00
QingPei Wang e169f82edf Add IT8721F support
only the serial port is tested, keyboard/mouse are gonna
to be tested later, it may also need some more patches
to make it work completely.

Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/204
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 04:47:26 +02:00
Peter Stuge 864839a3e8 util/crossgcc: Update gdb to 7.3.1
The previous version is no longer available.

Change-Id: I8126617cfe9addeb4778f002398abbcb4c73d2c7
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/214
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
2011-09-14 01:23:04 +02:00
Ruud Schramp bb41f50244 inteltool: added more device IDs
Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b
Signed-off-by: Ruud Schramp <schramp@holmes.nl>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/185
Tested-by: build bot (Jenkins)
2011-09-12 16:41:20 +02:00
Tobias Diedrich 4e22a3bc58 Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
uses the same acpi wakeup vector as S3.
Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
the power LED while sleeping.
acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
it is used in both romstage and ramstage after patch 3/3, whereas
i82371eb_early_pm.c is used only in romstage.
I used the name acpi_get_sleep_type instead of  acpi_is_wakeup_early
because I think acpi_is_wakeup_early is a bit misleading as a name since it
doesn't return a boolean value.

Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
added check for acpi_slp_type == 2 (resume from S2) should not
change behaviour of other boards:
northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:238:  acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
southbridge/via/vt8237r/vt8237r_lpc.c:239:  printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);

Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/188
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-12 15:56:12 +02:00
efdesign98 78834b794d Miscellaneous AMD F14 warning fixes
This commit adds in some more fixes to AMD F14 compile
warnings.  The change in the mtrr.c file is in prep-
aration for changes yet to com, but it is currently
innocuous.

Change-Id: I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/133
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-12 14:55:24 +02:00
Noe Rubinstein 03169d3e1c Replace while with do; while to avoid repetition
Cosmetic only; replaces some 'while' loops with 'do; while' loops to
avoid repetition.

Replacement performed by the Ruby expression:
t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
	"\\1do \\2\n\\1\\3;")

Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/183
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:48 +02:00
Patrick Georgi ac624a638d Crank up CPU speed on Intel Core and Core2 CPUs
The CPUs start on their slowest speed, and were left that way by
coreboot. This change will speed up coreboot a bit, as well as
systems that don't change the clock for whatever reason.

Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/176
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:30 +02:00
Stefan Reinauer 7981b940a6 Report GSE chipset and warn if the code has been compiled for the wrong chipset.
It would be nicer to unify the code so that it does all detection at runtime
instead of compile time (but that would also significantly increase code size)
so if someone else wants to give it a shot...

Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/184
Tested-by: build bot (Jenkins)
2011-09-09 11:40:04 +02:00
Rudolf Marek 8679e52b96 Add support utils for tracing
Following patch adds a userspace util genprof
which is able to convert the console printed
traces to gmon.out file used by gprof & friends.
The log2dress will replace the adresses in logfile
with a line numbers.

Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/179
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:27:57 +02:00
Rudolf Marek 7f0e93060e Add support for the tracing infastructure in coreboot.
The compiler is forced to emmit special functions on every
entry/exit of the function. Add a compile time option
to support it. Function entries will be printed in
the console. The CONFIG_TRACE has more documentation.

Patch for userspace tools will follow.

Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/178
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:26:47 +02:00
Kerry She f73535c089 AMD F14 Rev C0 update
Add AMD Family14 Rev C0 cpu id

Change-Id: Iacd1c7b20e889da61a2085188766285f27e5c018
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/160
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:10:29 +02:00
Kerry She 6209c8299a AMD SB800 southbridge update
This patch enables access to the registers of the hardware monitor
logical device in the superio via isa ports 0x295/0x296.
Previously this was not enabled in the SB8xx LPC device.
This is required for initialisation in init_hwm() in
src/superio/winbond/w83627hf/superio.c and also by OS-level
sensor monitoring such as lm-sensors to access temperature,
fan monitoring and control and voltage registers.
asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.

Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
Signed-off-by: Per Hansen <perh52@runbox.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/159
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:10:05 +02:00
Kerry She feed329a0c AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.

Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:08:57 +02:00
Wang Qing Pei 16d3ec6a58 Adjust some code/comment of sb700 sata init
The inline comment of sata_init function seems not placed correctly.
Rearrange it.

Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/186
Tested-by: build bot (Jenkins)
2011-09-04 12:22:09 +02:00
Wang Qing Pei f6e37316d0 Disable dev3 on ma78gm-us2h
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot.

Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/187
Tested-by: build bot (Jenkins)
2011-09-04 12:22:00 +02:00
Peter Stuge 0e8ee81edb buildgcc: Do not download GDB source code if run with --skip-gdb
Change-Id: Ida3680418fdd3136752d51cc19f3e14111c12131
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/175
Tested-by: build bot (Jenkins)
2011-08-29 22:42:24 +02:00
Sven Schnelle ebc28095ad Add a few more patterns to .gitignore
Change-Id: If7c1c6d9a96dd788bacee72b6e18a435069cad6e
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/172
Tested-by: build bot (Jenkins)
2011-08-27 09:44:50 +02:00
Sven Schnelle 054849dc6b Add dirty flag to git describe
git describe knows --dirty, which adds -dirty to the verion number
if the tree contains uncommited changes. We should add this flag
to make it obvious that the COREBOOT_VERSION might be misleading.
This is especially important as this version number is now used
in the SMBIOS data structures.

Change-Id: If4c608c7455e1bbf0cc530c6299fa00eb0fe4d58
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/173
Tested-by: build bot (Jenkins)
2011-08-27 09:44:34 +02:00
Sven Schnelle ff31692e08 X60/T60: remove obsolete dmi.h
Change-Id: Id0e8bcc1b93a629f0620b84a060d7ff99a82de78
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/174
Tested-by: build bot (Jenkins)
2011-08-26 22:35:43 +02:00
Sven Schnelle 164bcfdd1b Add automatic SMBIOS table generation
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/152
Tested-by: build bot (Jenkins)
2011-08-26 20:08:52 +02:00
Alec Ari bc081cdf6d Minor ma785gmt clean-up
Change-Id: I9e889a6c475fb3283fa11f8b3de5baaf54235589
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/167
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25 15:43:10 +02:00
Alec Ari e1562bdccb Fix up various dsdt.asl files
Change-Id: I46eb27847deb3a903ac9af347992a9954e50ff6e
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/166
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25 15:42:14 +02:00
Alec Ari 0e615007ec Remove dead code
Remove dead code, copy and pasted from
tilapia's mainboard.c file into various
asus mainboard.c files

Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/168
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-24 19:04:54 +02:00
Peter Stuge 09377b7d3f buildgcc: Remove all bashisms, making the script run also on BSD
Use sed instead of ${variable:start:length} and ${#variable}
Use single = in string comparisons
Use `eval echo '$'$variable` instead of ${!variable}
Use > file 2>&1 instead of &> file
Use readlink -f to expand the path of GCC configure

Change-Id: Idc7dfcea3922f55630a6855acdb19e36582708bd
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/165
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-08-21 08:47:00 +02:00
Peter Stuge 875b9b197f Use git describe to set KERNELVERSION
Change-Id: Id579b19fc38c7ca2b98ad1e87aaec71c070a9178
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/163
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-21 07:40:39 +02:00
Peter Stuge b98dbfb97e buildgcc: Fix typo in check for failed iasl build
Change-Id: I3e90b90e807ae775ac66af160a0f8547dcb3597a
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/164
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-21 07:39:57 +02:00
Sven Schnelle 6901b561eb Lenovo H8: Always clear audio mute
The mute bit is set by ACPI before poweroff/going to suspend.
So clear it after resume, to have working volume control
even if the ACPI doesn't clear it on resume.

OSPM should control Audio mute with ec bit 0x30:6, so it is
safe to clear this bit even if the user has audio muted.

Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/162
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2011-08-19 14:17:06 +02:00
Patrick Georgi b09e748f87 libpayload: export get_cbfs_header()
Keep in sync with coreboot's version.

Change-Id: I8a253446bd3b2ce9d05c6076a3f49f0260ecd5f9
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/158
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-18 22:02:53 +02:00
Sven Schnelle 8d0b86c9ab X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/Undocking
Change-Id: I674e5166f5fb7ba299e6f1231f30434a5bf731c5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/161
Tested-by: build bot (Jenkins)
2011-08-18 20:50:55 +02:00
Sven Schnelle d819853f85 export get_cbfs_header()
Change-Id: I4b6afcee3d0d169e03165a7fb48cfaef2e8253e2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-18 11:34:53 +02:00
Patrick Georgi c643fdd157 libpayload: Some more compatibility (for flashrom)
libpci defines an arbitrary set of PCI vendor IDs, flashrom uses the
Intel definition. Add it.

flashrom also requires inttypes.h, so add the OpenBSD version

Change-Id: I9bffd8193f635c375ac4d6b6eae8d3d876b95f5f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/154
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-17 16:26:20 +02:00