Use the references from the chipset devicetree as this makes the
comments superfluous.
Built all variants with BUILD_TIMELESS=1 and the resulting binaries
remain the same.
Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d
Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Instead of checking if there is more than one PCI segment group and
erroring out in that case during the build, add this requirement as a
dependency to the GENERATE_MP_TABLE Kconfig option. The mpspec.c source
file only gets included in the build if GENERATE_MP_TABLE is selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie532a401ad0161890d0fb4ca2889af022d5f6b47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The `d` flag used in .section is unknown in LLVM/clang 17 and fails
the build. It is also not documented in the ARM compiler manual.
The GNU assembler supports the `d` flag but it also seems to compile
without.
ARM compiler manual: https://developer.arm.com/documentation/101754/0621/armclang-Reference/armclang-Integrated-Assembler/Section-directives
GNU compiler manual: https://sourceware.org/binutils/docs/as/Section.html
`coreboot.rom` does not change between compiling a google skyrim board
with or without this patch. However the debug info for the following
three files in the build directory changes with this patch:
* build/verstage/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.o
* build/cbfs/fallback/verstage.elf
* build/cbfs/fallback/verstage.debug
Change-Id: Ie3735b72349b0cfdd27364a39bcdda390af7bfa5
Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79366
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Always use the high-level API region_offset() and region_sz()
functions. This excludes the internal `region.c` code as well
as unit tests. FIT payload support was also skipped, as it
seems it never tried to use the API and would need a bigger
overhaul.
Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Accessing RAM before mmu initialized is time consuming. During mmu
initialization, `mmu_init()` and `mmu_config_range()` write logs to the
console buffer and contribue the extra boot time.
This patch adds a kconfig option to move `mtk_mmu_init()` to
`bootblock_soc_early_init()`. When `EARLY_MMU_INIT` is enabled, mmu is
initialized before `console_init()` ready. So `mmu_init()` and
`mmu_config_range()` won't write logs to the console buffer and save the
boot time.
It saves about 65ms on Geralt with EARLY_MMU_INIT enabled.
Before:
0:1st timestamp 239,841 (0)
11:start of bootblock 239,920 (79)
12:end of bootblock 323,191 (83,271)
After:
0:1st timestamp 239,804 (0)
11:start of bootblock 239,884 (80)
12:end of bootblock 258,846 (18,962)
BUG=b:320381143
TEST=check timestamps in cbmem
Change-Id: I7f4c3c6c836f7276119698c6de362794cf4222a6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This reverts commit acbc491237.
Reason for revert: CB:79525 fixes the issue that led to the revert
by not maintaining the heap in the SMM-stored copy of ramstage at all.
Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Gothrax cannot boot into OS with a kernel loading failure.
Update eMMC DLL values to improve initialization reliability
How to get these values:
- Sending different speed TX/RX command/data signal to eMMC and check
the response is successful or not.
- Collecting above results from each eMMC model that project used.
- Analysing logs to provide a fine tuned DLL values.
BUG=b:310701323
TEST=Cold reboot stress test over 2500 cycles
Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
These are specific to the brox board, so moving devices to the brox
variant.
BUG=b:311450057,b:300690448,b:319058143
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
will check if this helps detect the storage device in the factory
Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Brox project has FW_CONFIG bits already set up in the project file for
the retimer and for storage, so make sure that the brox device tree
matches those settings.
BUG=b:311450057,b:300690448,b:319058143
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
will check if this helps detect the storage device in the factory
Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79854
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 32402941:
2024-01-08 19:53:43 +0000 - (treewide: Put the static keyword at the beginning of declarations)
to commit id 3d37d2aa:
2024-01-15 06:21:04 +0000 - (Makefile: Support FIRMWARE_ARCH=mock for firmware unit tests)
This brings in 2 new commits:
3d37d2aa Makefile: Support FIRMWARE_ARCH=mock for firmware unit tests
ffe3fb20 make_keyblock: Add support for omitting extension
Change-Id: I30425f0c50caf24800661568da8f72f6b4418d9c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
There is a mismatch in how PCI memory resources are allocated on Apollo
Lake with the current configuration. While the ACPI code expects
resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code
allocates them above, leading to the following error messages on Linux:
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window]
pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window]
pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window
pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window
pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff]
pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref]
Tested on up/squared with Linux kernel version 6.1.0.
Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS,
and by moving the UART base address into the expected range.
Thanks to Nico Huber for the help in writing this patch.
Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1
Signed-off-by: Reto Buerki <reet@codelabs.ch>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79957
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial support for multiple PCI segment groups. Instead of
modifying secondary in the bus struct introduce a new segment_group
struct element and keep existing common code.
Since all platforms currently only use 1 segment this is not a
functional change. On platforms that support more than 1 segment the
segment has to be set when creating the PCI domain.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Add new memory Micron MT62F1G32D4DR-031 WT:B.
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 2 (0010)
BUG=b:319778218
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79914
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that CONFIG_ECAM_MMCONF_BUS_NUMBER is non-zero when the
ECAM_MMCONF_SUPPORT Kconfig option is selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic102b7dca9ffebb2d384a068a1fb1f4b6fb6c5f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79933
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The Cavium CN81xx SoC selects ECAM_MMCONF_SUPPORT, but doesn't set a
value for ECAM_MMCONF_BUS_NUMBER which results in it defaulting to 0
which is wrong. Both the Cavium CN8100 SFF EVB and the OpenCellular
Elgon (GBCv2) mainboard specify 32 PCI buses in their Linux devicetree
files, so set the SoC's ECAM_MMCONF_BUS_NUMBER Kconfig option to 32 to
match this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79931
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Provide a default for the ECAM_MMCONF_LENGTH Kconfig option for the
ECAM_MMCONF_BUS_NUMBER option being set to 32.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I01e7da5d49f296dde2de41e23e86e3f49fe78193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The xeon_sp code worked around the coreboot allocator rather than using
it. Now the allocator is able to deal with the multiple IIOs so this is
not necessary anymore.
Instead do the following:
- Parse the FSP HOB information about IIO into coreboot PCI domains
- Use existing scan_bus and read_resource
- Handle IOAT stacks with multiple domains in soc-specific code
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The PCIE MMCONFIG base address value and size is updated correctly to
access the PCIE config space registers.
TEST=Verified that PCIE enumeration takes place in boot log
and config space registers are accessible.
Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79832
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The IOHUBS0 is a data fabric component which has a fabric id value
specific to SOC. Updated the fabric id for glinda SOC.
TEST=Verified that fabric ID is programmed correctly in boot logs.
Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79830
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Program SATA IOBP and enable clock gating after port enable
bits have been written.
The same registers are already set for DMI and PCIe.
TEST: Lenovo X220 still boots over SATA.
Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79146
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Describe the USB 'current' settings based on MRC.bin that converts
the USB trace length to a predefined register value.
MRC.bin decides which setting to use based on the PC type, mobile
or desktop, and the trace length.
Tested: Lenovo X220 still boots.
Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Currently autoport fills in USB current '0' if the detected setting
isn't one of the known settings. This works as 0 is a valid setting
from C point of view, but it's not supported on desktop PCs and on
mobile platform results in the lowest possible USB PHY gain. Thus
this might cause instabilities as the original firmware had stronger
USB drive currents and gain settings.
Add more known USB current fields to the map and generate a FIXME
as comment when the detected current isn't one of the known entries
instead of defaulting to 0.
Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78828
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
According to BWG the USB current setting 0 should not be used for
desktop boards. As autoport defaults to 0 if the USB current doesn't
match one of the lookup table entries most of the desktop boards in
tree have such a setting. Print an error to alert users of such boards
to update the USB current settings.
Tested: Lenovo X220 still boots.
Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78827
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since all devicetrees from lenovo/x220 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Janik Haag
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Since all devicetrees from asus/h61_series are using the reference names
for PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: I1ba2cb08e60cf806c5d749be15265e577a7abc25
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Since all devicetrees from asus/maximus_iv_gene-z are using the
reference names for PCI devices, remove the equivalent comments
documenting their function.
Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79967
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since all devicetrees from lenovo/t520 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: I307dbf7a7d6fc9086e868d8315ba7a66b94a24e7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
A recent update broke installation of commonlib headers with a relative
path in $(DESTDIR), which is the default. Make sure to install into the
right location in case we changed the current directory.
Change-Id: I61fa4aa0ecd0f81ee03ff89183e1b65e7875dea6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: ee53dfd07d (libpayload: Remove shell for loops in install Makefile target)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79908
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Correct bank1 to bank0
2. Adjust CLK duty
3. Fix abnormal power off setting
4. Change VDDE power off frame from VGL to VGH
Fixes: 0d50536("drivers/mipi: Add support for BOE_NV110WUM_L60 panel")
BUG=b:319398058
TEST=boot Ciri with BOE_NV110WUM_L60 and see firmware screen
Change-Id: I2f068ba0ec9dede3e3361b55c38a8eca8793905a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The IVO_T109NW41 will be the second source MIPI panel for Ciri.
BUG=b:319025360
TEST=boot Ciri with IVO_T109NW41 panel, see firmware screen
BRANCH=None
Change-Id: I9dc2228d39bb8bb048d1f37727c96b0ad621e912
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The MIPI panel BOE_NV110WUM_L60 will be used for Ciri, enable it.
Also remove the `mdelay(10)` after mtk_i2c_bus_init, because MTK
confirms this is not needed. Add mdelay(2) between VDD18 and VSP/VSN
to meet the panel datasheet.
BUG=b:308968270
TEST=Boot to firmware screen
BRANCH=None
Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78957
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Always use the high-level API region_offset() and region_sz()
functions. This excludes the internal `region.c` code as well
as unit tests. FIT payload support was also skipped, as it
seems it never tried to use the API and would need a bigger
overhaul.
Change-Id: Iaae116a1ab2da3b2ea2a5ebcd0c300b238582834
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Rename the segment group parameter of smbios_write_type41 from 'segment'
to 'segment_group' to be in line with the PCI specification.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie6ca0ce8b6b3b0357df72bafa2b6069132d0937e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79926
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I48b393913913db8436f5cbca04d7411e68a53cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Marvin Evers