Since PCH_DEVFN_PMC device is a PCI device that may be
hidden from enumeration, use SA_DEVFN_ROOT instead to
locate the SOC configuration.
Change-Id: I4b5195827fb32ec1dbd0bd6c9e243f4f9a4775ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets
removed from the root bus as leftover unused device. With change
903b40a8a4 ("soc/intel: Replace uses of dev_find_slot()"), all uses
of dev_find_slot() were replaced by pcidev_path_on_root() which relies
on scanning of root bus to find the requested device. Since PMC device
is removed from the root bus, pcidev_path_on_root() returns NULL for
it thus resulting in configuration being skipped for the PMC
ultimately resulting in S3 failures.
Since the PCH_DEV_PMC was just used to get to chip config, this change
replaces the use of PCH_DEV_PMC with SA_DEV_ROOT.
BUG=b:136861224
TEST=Verified that S3 works fine on hatch.
Change-Id: Ie5ade00ac2aca697608f1bdea9764b71c26e2112
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Dumping ME status displays wrong information if we disable Heci1 because
it is called after fsp notifies EndOfFirmware and disables Heci1. This patch
moves the ME status dump before fsp notify EndOfFirmware.
TEST=Boot to OS, check ME dump information
Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
At the end of device enable, print the ME f/w version number.
Before resume or loading payload, dump the ME's Host Firmware
Status registers.
BUG=b:131437724
BRANCH=none
TEST=Prints seemingly sane values on WHL and CML devices.
Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.
BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”
For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"
Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Iea56a6560bb23d48d19211304e57fc08e1c27fd6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26584
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to reduce BOM cost and board area for imaging solution, the
sensor requires a 19.2/24MHz reference clock from PCH. In addition to
that, having PCH to supply the sensor reference clock will prevent
dependency on CPU power management and also avoid level shifter cost.
Pch iSCLK is only required for CNP-LP with the camera sensor on the
platform.
BUG=None
TEST=Boot up into OS and read back PCH iSCLK programming through
iotools.
Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23367
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before OS boot up, the following actions need to be taken.
1. Lock down PMC/SPI/DMI/TCO register.
2. Disable Sideband Access.
3. Disable Heci interface.
4. Disable PMtimer base on config settings.
TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp
board.
Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21943
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
