Commit Graph

35575 Commits

Author SHA1 Message Date
Johnny Lin 496bd1555d drivers/ipmi: Add function read_data_string() to make code cleaner
Tested on OCP Tioga Pass.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I1da8abaa682af802e5cda65e5021069daf4ee717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-06-25 11:53:59 +00:00
Morgan Jang 6359d0661f mb/ocp/deltalake: Enable IPMI KCS
Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result.

TEST=Check if the BMC IPMI reponse data is correct or not.

Change-Id: I675060299b486986ebc39d8f714615b3e13de89a
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41023
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 11:53:47 +00:00
Jonathan Zhang ed624c7158 soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs
Support display of CPX-SP specific HOBs (when CONFIG_DISPLAY_HOBS
is selected, and UPD parameters (when CONFIG_DISPLAY_UPD_DATA is selected).

Such display is used for FSP debugging purpose. It adds small
amount of boot time.

Some UPD display log excerpts:
UPD values for SiliconInit:
  0x04: BifurcationPcie0
  0x03: BifurcationPcie1

Some HOB display log excerpts:
=== FSP HOBs ===
0x758df000: hob_list_ptr
0x758df000, 0x00000038 bytes: HOB_TYPE_HANDOFF
0x758df038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41348
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 11:53:34 +00:00
Sheng-Liang Pan eba0433b17 mb/google/octopus/variants/bobba: fix disable_xhci_lfps_pm by sku
due to overridetree.cb set disable_xhci_lfps_pm = 0,
need correct condition expression to let function work.

BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I53621d7674a531adfa40e8703cb2cd01c50376b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42564
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 11:53:12 +00:00
Furquan Shaikh 2ef3b2df1f mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table
This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.

A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 08:10:04 +00:00
Furquan Shaikh 8302585c15 mb/google/zork: Add support for WiFi power sequencing
This change replaces variant_wifi_romstage_gpio_table() with
variant_pcie_power_reset_configure() to handle the reset and power
sequencing for WiFi devices pre- and post- v3 version of schematics.

These are the requirements that need to be satisfied:
1. As per PCI Express M.2 Specification Revision 3.0,
Version 1.2, Section 3.1.4 "Power-up Timing", PERST# should stay
disabled until `TPVPGL` time duration after device power has
stabilized.  Value of TPVPGL is implementation specific.
2. For Intel WiFi chip, it is known to get into a bad state if the
above requirement is violated and hence requires a power cycle.
3. On pre-v3 schematics:
  - For both dalboz and trembyle references, GPIO42 drives
  WIFI_AUX_RESET_L which is pulled up to PP3300_WIFI.
  - For both dalboz and trembyle references, PP3300_WIFI is controlled
  using GPIO29. This pad gets pulled high by default on PWRGOOD
  because of internal pull-up. But, at RESET# it is known to have a
  glitch. When GPIO29 gets pulled high, it causes WIFI_AUX_RESET_L to
  be pulled high as well. This violates the PCIe power sequencing
  requirements. Hence, for pre-v3 schematics on both dalboz and
  trembyle, following sequence needs to be followed:
   a. Assert WIFI_AUX_RESET_L.
   b. Disable power to WiFi.
   c. Wait 10ms to allow WiFi power to go low.
   d. Enable power to WiFi.
   e. Wait 50ms as per PCIe specification.
   f. Deassert WIFI_AUX_RESET_L.
4. On v3 schematics:
   - For trembyle: WIFI_AUX_RESET_L is driven by GPIO86 which has an
   internal PU as well as an external PU to PP3300_WIFI.
   - For dalboz: WIFI_AUX_RESET is driven by GPIO29. This is active
   high and has an internal PU. It also has an external 1K PD to
   overcome internal PU.
   - For both dalboz and trembyle references, PP3300_WIFI is
   controlled by GPIO42 which has an internal PU and external
   PD. Trembyle schematics have a comment saying strong PD of 2.2K but
   the stuffed resistor is a weak one (499K). ON dalboz, it uses a
   weak PD (which doesn't look correct and instead should be a strong
   PD just like trembyle). Having a strong PD ensures that the WiFi
   power is kept disabled when coming out of G3 until coreboot
   configures GPIO42 as high.
   - Thus, for v3 schematics, following sequence needs to be followed:
    a. Assert WIFI_AUX_RESET{_L} signal.
    b. Enable power to WiFi.
    c. Wait 50ms as per PCIe specification.
    d. Deassert WIFI_AUX_RESET{_L} signal.

BUG=b:157686402, b:158257076
TEST=Verified that QCA and AX200 cards both continue working. Tested
QCA on Dalboz and Trembyle. Tested AX200 on morphius.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532131ee911d5efb5130d8710f3e01578f6c9627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42738
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 08:08:37 +00:00
Furquan Shaikh 462f3ed111 mb/google/zork: Update ramstage GPIOs for v3 schematics for dalboz reference
This change updates the baseboard GPIO table in ramstage to match
v3 version of dalboz reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.

BUG=b:157165628, b:157744136, b:157743835
TEST=Compiles

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If9d0e35801f9f9b15eddeb4ec7068fed6d401307
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251394
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Auto-Submit: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 08:08:15 +00:00
Furquan Shaikh da459c46bd mb/google/zork: Update ramstage GPIOs for v3 schematics for trembyle reference
This change updates the baseboard GPIO table in ramstage to match v3
version of trembyle reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.

BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1d6ee2e995c1fca229c20ea63da9a45fb89f64a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251393
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 08:08:05 +00:00
Furquan Shaikh c699255ba5 mb/google/zork: Update _v3 romstage and wifi GPIO tables for dalboz
This change updates _v3 version of romstage and wifi GPIO tables
to match v3 schematics.

BUG=b:157165628, b:157744136, b:157743835
TEST=Compiles

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id8b46fcb4552af6eda5b50224b0557bae37f9ebd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251392
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42723
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 08:07:51 +00:00
Furquan Shaikh 8ae77f62cc mb/google/zork: Update _v3 romstage and wifi GPIO tables for trembyle
This change updates _v3 version of romstage and wifi GPIO tables to
match v3 schematics.

BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic605559b3226e2ad9b5b3f3fa45c4aa9f9b5fe22
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251391
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42722
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 08:07:39 +00:00
Furquan Shaikh 996fdc0057 mb/google/zork: Prepare variants for v3 schematics
This change updates variant_romstage_gpio_table() and
variant_wifi_romstage_gpio_table() to support v3 version of schematics
for dalboz and trembyle reference designs. gpio_set_stage_rom and
gpio_set_wifi are divided into two groups:
a) Pre-v3 (GPIO table for pre v3 schematics):
 * gpio_set_stage_rom_pre_v3
 * gpio_set_wifi_pre_v3
b) v3 (GPIO table for v3+ schematics):
 * gpio_set_stage_v3
 * gpio_set_wifi_v3

Currently, both _v3 is a copy of _pre_v3, but will be updated in
follow-up CLs to make it easier to identify what changed from _pre_v3
to _v3.

BUG=b:157088093, b:154676993, b:157098434, b:157165628, b:157744136, b:157743835
TEST=Compiles

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I444875d93100c2f2abdb6dec4312861fd89d9b78
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251390
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42721
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 08:06:13 +00:00
Furquan Shaikh 624c1ca04e mb/google/zork: Drop RAM_ID configuration from romstage gpio table
RAM_ID GPIOs are configured by ABL based on the information added to
APCB. coreboot does not need to configure these pads. This change
drops the RAM_ID configuration from trembyle baseboard. Dalboz never
really configured RAM_IDs in coreboot.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1dfcc3c185304d917ab4386920445ba0119ac69
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252710
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 07:59:30 +00:00
Furquan Shaikh 39a6145e41 mb/google/zork: Move variant_early_gpio_table to gpio_baseboard_common.c
This change moves the GPIOs that need to be configured for early
access in coreboot to early_gpio_table[] in
gpio_baseboard_common.c. These GPIOs include:
* Pads to talk to EC
* Pads to talk to TPM
* Pads to talk to serial console

These should be configured in the first stage that runs coreboot
i.e. in case of VBOOT_STARTS_BEFORE_BOOTBLOCK, it should be done as
part of verstage (which starts on PSP), else it should be done as part
of bootblock (which is the first stage that runs on x86).

This change drops GPIO_137 from early_gpio_table since that is not
really required in early stages.

BUG=b:154351731
TEST=Verified that trembyle still boots.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifbdbb02cbfc65ddb68f0ae75cf4b1f2ea1656b91
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252709
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-25 07:59:23 +00:00
Edward O'Callaghan 28da35417b soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define
Align support for enable wake-on-usb attach/detach as was
introduced in Skylake in
 `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.

BUG=b:159187889
BRANCH=none
TEST=none

Change-Id: Ie63e4f1fcdea130f8faed5c0d34a6a96759946b6
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42716
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25 04:21:10 +00:00
Felix Held f9d3d33a55 mb/amd/mandolin: maximize CBFS size
Change-Id: Ib829da0972bb7ec98f66fe8fe683289d91ad58dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-24 19:01:21 +00:00
Sumeet R Pawnikar d92d0e24ae jasperlake: enable DPTF functionality for dedede
Enable DPTF functionality on jasperlake based dedede platform

BRANCH=None
BUG=None
TEST=Built for dedede system

Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 16:03:26 +00:00
Aaron Durbin 8c28e51a16 soc/amd/picasso: fix host bridge bus numbers
The host bridge's resources covering bus numbers assumed
256 buses were being decoded. However, MMCONFIG was only
covering 64 buses. This results in Linux complaining:

    acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000
    [bus 00-3f] only partially covers this bridge

When retrieving the host bridge's resources fix up the
bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't
keep IASL from complaining when trying to do this statically.

BUG=b:158874061

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-24 13:59:15 +00:00
Lucas Chen c1bb32f869 mb/google/zork: Add UPD xhci0_force_gen1 for Trembyle and Ezkinil
Add UPD xhci0_force_gen1 for Trembyle and Ezkinil.
The default setting is set to disable, and set enabled for Ezkinil.
Trambyle -> set default as disable.
Ezkinil  -> set enable by request.

BUG=b:156314787
BRANCH=trembyle-bringup
TEST=Build. Verified the setting will be applied on Ezkinil/Trembyle.

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2216090
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-24 12:43:28 +00:00
Chris Wang ab3947a021 soc/amd/picasso: Add UPD xhci0_force_gen1
Adding xhci0_force_gen1 UPD to force USB3 port to gen1.

BUG=b:156314787
BRANCH=trembyle-bringup
TEST=Build.

Cq-Depend: chrome-internal:3013435
Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 12:43:20 +00:00
William Wei 34053fab21 mb/google/volteer/malefor: Update overridetree.cb
1) Based on malefor schematics, disable unused I2C port, USB port, TBT
   PCIe
2) Add audio device to the tree

BUG=b:150653745, b:154973095
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Boot to kernel and check the devices' function worked properly.

Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42246
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:58:47 +00:00
Nick Vaccaro fbb023245b volteer: Create volteer2 variant
Create the volteer2 variant of the volteer reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

Modified to alphabetize and update to duplicate latest volteer changes
currently in the review and merge pipeline.

Added the following missing files from the variants/volteer2/ folder:
 - gpio.c
 - include/variant/acpi/dptf.asl
 - acpi/mipi_camera.asl
 - Makefile.inc
 - memory/dram_id.generated.txt
 - memory/Makefile.inc
 - memory/mem_list_variant.txt
 - overridetree.cb

BUG=b:159135047
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOLTEER2

Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42605
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:53:19 +00:00
John Zhao 8528867088 soc/intel/tigerlake: Fix unresolved symbol CDW1 error
The dmesg shows unresolved symbol CDW1 with AE_NOT_FOUND error after
booting to kernel. Fix the error by properly creating the buffer field
CDW1 to cover all errors scenarios.

BUG=b:140645231
TEST=Verified no AE_NOT_FOUND error related to \_SB.OSC.CDW1.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ibfe677f87736ce1930e06b9cd649791977116012
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42693
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:53:10 +00:00
Elyes HAOUAS fac2893584 soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
The PCI_INTERRUPT_LINE register is one byte wide.
Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.

Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:52:28 +00:00
Angel Pons a23aff3651 src: Report byte-sized access for GPE0
According to the ACPI specification, version 6.3:

    OSPM accesses GPE registers through byte
    accesses (regardless of their length).

So, reporting dword-sized access is wrong and means nothing anyway.

Tested on Asus P8Z77-V LX2, Windows 10 still boots.

Change-Id: I965131a28f1a385d065c95f286549665c3f9693e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:50:50 +00:00
Angel Pons 0623b01036 sb/intel/bd82x6x: Align mei_recv_msg() functions
They only differ in rather small details, so we can iron them out.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I01907f1b8576e82c74b7beeea31ae8ee3e2cc773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42010
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:50:12 +00:00
Matt DeVillier c08d4c5c55 soc/amd/stoneyridge: Correct ACPI CPU string prefix
Commit 9550e97 [acpi: correct the processor devices scope] changed
the default CPU scope from _PR to _SB, but the default prefix in
Stoneyridge's Kconfig was missed, leading to ACPI errors for
'AE_NOT_FOUND for object \_PR.P00n.' Fix the default prefix and
eliminate the errors reported in dmesg.

Test: boot Linux w/5.3 kernel on google/liara, check for errors

Change-Id: I5611b6836062a0a9f90036d7fe40cd98bd730af3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-24 11:50:00 +00:00
Kyösti Mälkki c3c55210ee ACPI: Replace smm_setup_structures()
Except for whitespace and varying casts the codes were
the same when implemented.

Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.

Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24 11:49:15 +00:00
Kyösti Mälkki 5daa1d3898 ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
These are the simple cbmem_find() cases. Also drop the redundant
error messages.

Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-24 11:48:38 +00:00
Kyösti Mälkki e37459ed64 ACPI: Add framework for GNVS initialisation
Provide common initialisation point for setting up
GNVS structure before first SMI is triggered.

Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42423
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:46:26 +00:00
Zhuohao Lee cf06124cc6 volteer: Create delbin variant
Create the delbin variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:158797761
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_DELBIN

Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-24 05:07:34 +00:00
Zhuohao Lee 36aaddf7d7 util/mainboard/google/volteer: Add dptf.asl to the template
The dptf.asl is needed when creating a new volteer variant, otherwise,
it will make the variant build failed. The error could be found from
this link: https://review.coreboot.org/c/coreboot/+/42709

BUG=b:158797761
TEST=Generate the Delbin correctly

Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Ib4059df9e08d6a1dba88f0299bb39c8c6ae406ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-24 05:07:27 +00:00
Felix Held 9e92c1d787 mb/amd/mandolin: resize EC FMAP section to match EC firmware size
The EC firmware is 128k including its header, so there's no need to
reserve another 4k for the header.

TEST=Mandolin still boots.

Change-Id: Id3a7a087bf37461ca8ad3da9a809f13d7f0d570c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42705
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 01:18:56 +00:00
Paul Fagerburg 8af1bcd38f hatch: Create wyvern variant
Create the wyvern variant of the puff reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:158269582
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_WYVERN

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 23:23:30 +00:00
Edward O'Callaghan 394b5fabf4 hatch: Create faffy variant
Create the faffy variant of the puff reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

V.2: Manually modified to keep Kconfig sorted.

BUG=b:157448038
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_FAFFY

Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 22:46:14 +00:00
Martin Roth cfc170b213 src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor.  With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.

This change will add these files to verstage only if the verstage
architecture is X86 - either 32 or 64 bit.

BUG=b:158124527
TEST=Build and boot on Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I797b67394825172bd44ad1ee693a0c509289486b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 21:28:40 +00:00
Felix Held f3343f2560 mb/amd/mandolin/acpi: drop gpe.asl
Change-Id: I366108334006c81a4d5fb193f583a1e83f7c1456
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-23 18:39:35 +00:00
Furquan Shaikh baf1364f79 mb/google/zork: Add support for fingerprint device
This change adds support for fingerprint device in overridetree for
the following variants:
1. berknip
2. morphius
3. trembyle

Generates the following node in SSDT1:
    Scope (\_SB.FUR1)
    {
        Device (CRFP)
        {
            Name (_HID, "PRP0001")  // _HID: Hardware ID
            Name (_UID, Zero)  // _UID: Unique ID
            Name (_DDN, "Fingerprint Reader")  // _DDN: DOS Device Name
            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                Return (0x0F)
            }

            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
            {
                UartSerialBusV2 (0x002DC6C0, DataBitsEight, StopBitsOne,
                    0x00, LittleEndian, ParityTypeNone, FlowControlNone,
                    0x0040, 0x0040, "\\_SB.FUR1",
                    0x00, ResourceConsumer, , Exclusive,
                    )
                GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000,
                    "\\_SB.GPIO", 0x00, ResourceConsumer, ,
                    )
                    {   // Pin list
                        0x0006
                    }
            })
            Name (_S0W, 0x04)  // _S0W: S0 Device Wake State
            Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
            {
                0x0A,
                0x03
            })
            Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
            {
                ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
                Package (0x01)
                {
                    Package (0x02)
                    {
                        "compatible",
                        "google,cros-ec-uart"
                    }
                }
            })
        }
    }

BUG=b:147853944

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7ccb3633332ce3e388293872af7b22f1867c8465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-23 17:42:35 +00:00
Edward O'Callaghan 5d33d03d3f util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB ports
Switch USB2 port1 and port3 due to circuit change from rev0.

BUG=b:154071868,b:154585046,b:156429564
BRANCH=none
TEST=none

Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 01:15:14 +00:00
Edward O'Callaghan b6737fc54a util/mb/google/tmpl/puff: Import overridetree.cb copy
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 01:13:12 +00:00
Zhuohao Lee 7587526583 palkia: separate the gpio pins control for the second touch
There are two touch screen controllers on the Palkia device.
One is on the lid; another is on the base. To support
the different control path (for example: turning off the base's
touch event when we don't want to use it however still keeping
the lid's touch event), we use the different gpio pins to control
the second touch. As a result, we need to modify the devicetree
to adopt this change. With this change, we can control the
primary and secondary touch screen controller respectively.

BUG=b:149714955
TEST=lid/base touch screen works correctly

Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-23 00:54:09 +00:00
Edward O'Callaghan 4229dfc215 util/mb/google/tmpl/puff: Generate correct gpio muxing
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: Iae4fe48b6a3df730b2334cb1f32b35addc90bec0
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 00:06:56 +00:00
Edward O'Callaghan 6ceca5d064 util/mb/google/tmpl/puff: Fix include paths for gen board
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: Ifa5cd021ae37d61ddb9eb9bf6a970a931058e33c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 00:06:43 +00:00
Edward O'Callaghan e54487f207 mb/google/hatch: Make puff and variants share common mainboard.c
Here we consolidate some of the mainboard.c duplication between
Puff and it's variants.

Customizations can be done later via introducing a devicetree
parameterisation.

BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 00:06:28 +00:00
Marshall Dawson 6e5e24e2b3 cbmem: Remove IDs for TSEG and BERT
Remove the changes added in
  commit 80df052d3 "cbmem: Add IDs for TSEG and BERT table data"

No platform uses either ID.  TSEG in cbmem is incompatible with stage
cache.  BERT reserved data in cbmem is unusable in Linux.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I5501424bfeb38d5ff5432678df9e08b4c16258f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42532
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 22:57:13 +00:00
Marshall Dawson 03743b7fa3 soc/amd/picasso: Set BERT_SIZE to 0 when no table generated
BUG=b:136987699
TEST=Verify no region reserved when CONFIG_ACPI_BERT=n

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I95d511e454e7f2998e46e14112eea5e8b09d59b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-22 22:56:59 +00:00
Marshall Dawson d91d2df2cc soc/amd/picasso: Convert BERT reserved region from cbmem
Picasso's BERT region should not have been moved to cbmem in commit
  901cb9c "soc/amd/picasso: Move BERT region to cbmem".  This
causes an error of "APEI: Can not request [] for APEI BERT registers.

FSP has been modified to set aside a requested region size for BERT,
simiar to TSEG.  Remove the cbmem reservation and locate the region
by searching for the HOB.

BUG=b:136987699
TEST=Check that BERT is allocated

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 22:56:34 +00:00
Elyes HAOUAS a138366f3a src/mainboard: Remove unused include 'sandybridge.h'
Change-Id: I9356a56c34d1c6746cf8acfe931386ffed58ba74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 16:30:48 +00:00
Felix Held 96a7a835bf mb/amd/mandolin/hda_verb: use AZALIA_RESET and AZALIA_PIN_CFG macros
TEST=Doesn't change the resulting binary for BUILD_TIMELESS=1.

Change-Id: I9fccc53c3d56116027e28a9eec6ec27202017a79
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 16:24:27 +00:00
Angel Pons 013711b533 sb/intel/i82801ix/fadt.c: Use acpi.h definitions
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I284eec23a8804f7bb18d2ef493c1200c197c109e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22 14:49:49 +00:00
Angel Pons aaa8ab7ac3 sb/intel/i82801{ix,jx}/hdaudio.c: Use `Azalia` in printk
For some reason, one printk statement begins with `HD Audio` instead of
the more common `Azalia`. Change the different prefix for consistency.

Change-Id: Ia79e340f331b9186cc09b04f925ff9d94204955e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-06-22 14:49:24 +00:00