With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This fixes the following issues:
bincfg.l: In function ‘parsehex’:
error: declaration of ‘val’ shadows a global declaration
bincfg.y: In function ‘generate_binary_with_gbe_checksum’:
error: comparison of integer expressions of different signedness
bincfg.y: In function ‘yyerror’:
bincfg.y:408:28: error: unused parameter ‘fp’
bincfg.y: In function ‘main’:
bincfg.y:452:15: error: unused variable ‘pos’
bincfg.y:451:16: error: unused variable ‘c’
BUG=None
TEST=Build outputs and make sure they're identical.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I60039b741c226a6b6ba53306f6fa293da89e5355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Gets rid of these 4 warnings:
archive.c: In function ‘set_file_name’:
warning: comparison of integer expressions of different signedness
archive.c: In function ‘add_file’:
warning: comparison of integer expressions of different signedness
archive.c: In function ‘archive_files’:
warning: comparison of integer expressions of different signedness
archive.c: In function ‘convert_endian’:
warning: comparison of integer expressions of different signedness
BUG=None
TEST=Build and run
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I57ee8b31bbc9e97168e3b818c4d053eadf8a4f84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Add method to disable warnings as errors
- Add help target
- Add phony targets to .PHONY
BUG=None
TEST=make all; make help; make all WERROR=""
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icd0cfd3e2579c9016ebb616e371d1076a5a171b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fixes these warnings:
warning: alignment 1 of 'struct _psp_directory_table' is less
than 16 [-Wpacked-not-aligned]
warning: alignment 1 of 'struct _psp_combo_directory' is less
than 16 [-Wpacked-not-aligned]
In function 'find_register_fw_filename_bios_dir':
warning: implicit conversion from 'enum _amd_fw_type' to
'amd_bios_type' {aka 'enum _amd_bios_type'} [-Wenum-conversion]
BUG=None
TEST=Build and verify binaries are identical.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I761d9893ac6737b42af96c4b2a57c5a4fc61ab05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Additionally to the PCI IDs of Cezanne it also handles the Renoir ones.
The main difference between those two is that Renoir has two core
complexes while Cezanne only has one core complex. I haven't seen
incompatible changes between those two though, so for example the fabric
IDs are the same and the one that's only present in Renoir is just not
used in Cezanne. Also adding the ACPI parts for those don't have
anything to do with those differences.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b2517bc15d872f41183a33857333f1972ff2cb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It’s good practice to put the unit into the name.
Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Only the call in `spi_flash_cmd_write_page_program` uses non-constant
values for the array length. However, the value for `data_len` has an
upper bound: `flash->page_size` is set to `1U << vi->page_size_shift`
which depends on the flash chip vendor info, and the largest value it
can currently have is 8. Thus, the maximum page size is currently 256.
Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on
the amount of data that can be written in one command. Then, use this
value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also,
add a check to prevent buffer overflow problems. Finally, ensure that
the `spi_flash_cmd_write_page_program` function always writes no more
than 256 bytes of data when using the `spi_flash_cmd_write` function.
Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works.
Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because
Lynxpoint uses a different value. Also drop unnecessary includes.
Tested with BUILD_TIMELESS=1, Google Tidus remains identical.
Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use `lp_gpio.h` from Lynxpoint instead. Subsequent commits will update
the mainboards and then drop all GPIO code from Broadwell.
Tested with BUILD_TIMELESS=1, Google Tidus remains identical.
Change-Id: Idef89037c2ca781ac3e921abb4b3dc3f7c4b3b5f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50079
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `GPIO_OUT_HIGH` macro is not present on Lynxpoint headers.
Change-Id: I12dd065bee49097c602febf18c6c9940ecec5106
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50078
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Auron Paine remains identical.
Change-Id: I00b9184fe6f002c3e089c9fbc815862d60e7694f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50068
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Second pass GPIO configuration to enable the non-native function
GPIOs based on the guybrush Proto 0 reference schematic 0210.
BUG=b:177909472
TEST=builds
Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Kyösti Mälkki