Commit Graph

36279 Commits

Author SHA1 Message Date
Angel Pons e80d17f602 soc/intel/baytrail: Retype some pointers
This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 10:17:40 +00:00
Ravi Sarawadi e4109ff54f soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per
BWG(611569) Rev 0.8: section 4.5.3.2.2

BUG=none
TEST=Boot to OS and check C-State latencies
"cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}"

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43316
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 04:46:44 +00:00
Elyes HAOUAS 7cd8c79177 src/include/ramdetect.h: Add missing includes
Change-Id: I142f88aae67237ce6777f7f9e8849bae589beeb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:25:57 +00:00
Elyes HAOUAS c354599a53 payloads/libpayload/drivers/usb/usb.c: Remove whitespace before tab
Change-Id: Iba73ae4d89cef94f238e9a74300f6088669f355b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:25:25 +00:00
Elyes HAOUAS 81bebc8374 payloads/libpayload/curses/menu/eti.h: Remove unneeded whitespaces
Change-Id: Ia77c5be4b22740f88fb9c11bff95036adbd8145f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:25:16 +00:00
Elyes HAOUAS beaf9443aa payloads/libpayload/arch/arm/cpu.S: Remove whitespaces before tab
Change-Id: I2960f95937db23aa3a38ca64085728e6d10968f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:25:00 +00:00
Elyes HAOUAS e4d31061d7 payloads/external/tint/Makefile: Remove whitespaces before tab
Change-Id: Ie08e92778e029b962cf0ed5f95ab740458e82fc5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:24:51 +00:00
Elyes HAOUAS e1d1fe454c nb/intel/ironlake/raminit.c: initialize 'reply.command'
This to silent a bug found using gcc-10.
src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma':
src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized]
 1805 |  if (reply.command != (MKHI_SET_UMA | (1 << 7)))
      |      ~~~~~^~~~~~~~
cc1: all warnings being treated as errors

Change-Id: I0d13de549b6d428ac3675ee3f91eb5e42aeb25e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 01:23:49 +00:00
Angel Pons eecd6843a2 nb/intel/haswell/hostbridge_regs.h: Clean up registers
Add missing registers and sort them by ascending offsets.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I98f836668144032d920b56afff878acc0a58ed82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-25 01:22:28 +00:00
Elyes HAOUAS 28db21c462 mb/getac/p470/acpi_tables.c: Remove wrong comment
Change-Id: I85c20d282949b51efd7cdd6f6e79b0b84ff62e2b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:21:39 +00:00
Elyes HAOUAS e65280cbef autoport/bd82x6x.go: Remove generated extra line
Change-Id: I48125b7efd599b6a6718d7353156217df874d490
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25 01:16:58 +00:00
Angel Pons dd46dfa703 sb/intel/bd82x6x: Use common irqlinks.asl
Both files are identical, so we only need one copy in the tree.

Change-Id: I07d7429caca7f6211a186b770c3608f642d4f269
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43159
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 00:12:06 +00:00
Sumeet R Pawnikar 1a62150709 soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU
Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.

BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.

Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 00:07:36 +00:00
Derek Huang 60f178db65 soc/intel/tigerlake: Update Tiger Lake SA IDs
This patch updates Tiger Lake SA DID and report platform. According to
doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below
definitions of SA ID for TGL-UP4 skus:
TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h
TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h

Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 00:07:20 +00:00
Felix Held 0b5a6143ea soc/amd/picasso: mark usb2_phy_tune struct as packed
Since the binary layout of this struct matters, it should be marked as
packed. Since all struct elements are uint8_t, this shouldn't result in
a different layout though.

BUG=b:161923068

Change-Id: I6a390c3a3f35eaf8a72928b4cef0e9f405770619
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43780
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 23:55:57 +00:00
Maxim Polyakov d46c023a22 mb/supermicro/x11-lga1151: Clean up gpio.h
- remove comments (except the GPIO group), because it does not contain
  useful information that helps to understand the circuit, which we do
  not have;
- remove empty lines between macros;
- use a shorter PAD_CFG_GPI_INT() macro instead of
  PAD_CFG_GPI_TRIG_OWN() to set DRIVER mode.

Change-Id: Ia7111341aab6f400da70d936849e4d4c9406905b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-24 23:42:41 +00:00
Maxim Polyakov 16fd9d6864 supermicro/x11-lga1151/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros, which were
hidden in the comments. To do this, the following command was used:

./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h

./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h

This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":

CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG

Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F,
remains identical.

Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35679
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 23:41:48 +00:00
Maxim Polyakov ae9ddd465d supermicro/x11-lga1151/gpio: 3/4 Fixes some field macro
Fixes some bit fields to convert to target macros PAD_CFG_*() macros.

This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":

CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG

Change-Id: I291f5f0f34505c466b610aa4049c8cc35937d140
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42918
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 23:40:45 +00:00
Maxim Polyakov 68c7eff5fe supermicro/x11-lga1151/gpio: 2/4 Exclude fields for PAD_CFG
This patch excludes bit fields that should be ignored [1] in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:

./intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h

/intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h

[1] ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
    Disable (bit 9:8) for the native function, because it does not
    affect the pad in this mode.

This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":

CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG

Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42917
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 23:39:33 +00:00
Tim Wawrzynczak 97f69a1a94 mb/google/volteer: Remove unused dptf.asl files
In the middle of the Great DPTF Refactor of 2020, new volteer variants
were added, but their dptf.asl files are no longer used, so delete them.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I52f2042aa870a29026eb9fe122340ad07654e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-24 23:27:43 +00:00
Tim Wawrzynczak ac2282e907 util/mb/google/volteer: Delete dptf.asl
Since we are not using raw ASL files anymore for DPTF, delete the
template file too, so that it does not keep getting added for new
board variants.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia128989c64b8c02759c326431b4ee30fd2b483e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-24 23:27:39 +00:00
Angel Pons 464519769b assert.h: Do not use __FILE__ nor __LINE__ on timeless builds
When refactoring, one can move code around quite a bit while preserving
reproducibility, unless there is an assert-style macro somewhere... As
these macros use __FILE__ and __LINE__, just moving them is enough to
change the resulting binary, making timeless builds rather useless.

To improve reproducibility, do not use __FILE__ nor __LINE__ inside the
assert-style macros. Instead, use hardcoded values. Plus, mention that
timeless builds lack such information in place of the file name, so that
grepping for the printed string directs one towards this commit. And for
the immutable line number, we can use 404: line number not found :-)

Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-24 23:23:54 +00:00
Angel Pons 579e096ec8 nb/intel/sandybridge: Put host bridge registers into its own file
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: Ibfaecd6ab94d2caae9804bb827ce8e48a2166d35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24 23:19:36 +00:00
Angel Pons e220e31127 nb/intel/haswell: Put host bridge registers into its own file
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I1d3a32a9386c0dee65eea6f9d0a2520d5e800db1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43690
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 23:18:27 +00:00
Angel Pons ad247ac5d8 device/pci_device.c: Do not complain about disabled devices
One would expect disabled devices to not be present. So, don't print
misleading warnings about it, because it only confuses people.

Change-Id: I0f14174a1d460a479dc9f15b63486f4f27b8f67c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-24 23:12:07 +00:00
Maxim Polyakov dfa051a21d supermicro/x11-lga1151/gpio: 1/4 Decode raw register values
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:

./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h

./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h

[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643

This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":

CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG

Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F,
remains identical.

Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42916
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 22:56:00 +00:00
Maxim Polyakov 06299a776f soc/intel/common/gpio_defs: Remove unused macro for NF
Since the bufdis parameter (bit 9:8 in Pad Configuration DW0 register)
does not affect the pad in native function mode,
PAD_CFG_NF_BUF_IOSSTATE_IOSTERM() macro is not required to configure
the pad. This macro has not been used, so deleting it will not affect
anything.

Change-Id: Icce6f130308dbe7032b99539f73688bae8ac17e0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42913
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 22:52:44 +00:00
Maxim Polyakov 97b5b3b3ca soc/intel/common/gpio_defs: Undo set TxDRxE in GPI_TRIG_OWN()
IO Standby State can use various settings independently of
PAD_CFG_GPI_TRIG_OWN (). Instead, use other existing macros to set this
parameter:

 - PAD_CFG_GPI_IOSSTATE_TRIG_OWN()
 - PAD_CFG_GPI_TRIG_IOS_OWN()

Change-Id: I0f5fbd79f892981eb4534f50ac96a7d0c190f59e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42912
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 22:52:00 +00:00
Maxim Polyakov fb2e71137a soc/intel/common/gpio_defs: Improve some GPI macros
The patch updates existing macros for the GPI:

  - PAD_CFG_GPI_IOSSTATE_IOSTERM()
  - PAD_CFG_GPI_IOSSTATE()

to allow the user to set the RX Level/Edge Configuration (trig) and
the Host Software Ownership (own) fields in addition to IO Standby State
(iosstate) and IO Standby Termination (iosterm) in the pad configuration
using these macros.

Change-Id: I8a70a366e816d31720d341a5d26880dc32ff9b8d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-24 22:44:34 +00:00
Matt Papageorge ab83b43b34 soc/amd/picasso/sb: Gate FCH AL2AHB clocks
Gate the A-Link to AHB Bridge clocks to save power. These
are internal clocks and are unneeded for Raven/Picasso.
This was previously performed within the AGESA FSP but this
change relocates it into coreboot.

BUG=b:154144239
TEST=Check AL2AHB clock gate bits at the end of POST before and
after change with HDT.

Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-24 22:01:51 +00:00
John Zhao 9857c90685 superio/common: Avoid NULL pointer dereference
Coverity detects dereferencing a pointer that might be "NULL" when
calling report_resource_stored. Add sanity check for dev to prevent
NULL pointer dereference.

Found-by: Coverity CID 1419488

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I03efad87ba761e914b47e3294c646335cfbaed24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-24 21:21:09 +00:00
Felix Held 7f107b472a soc/amd/picasso/fsp_params: add missing newline between functions
Change-Id: If5d798a410f092e0ce99c16c84809b6b2e30cc2e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43779
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 20:29:36 +00:00
Felix Held a319ac3a19 soc/amd/picasso/fsp_params: add asserts for descriptor count
With the updated FSP UPD headers there are enough DXIO descriptor slots
in the UPD, so we can now add asserts to make sure that the mainboard
doesn't pass more DXIO/DDI descriptors than the UPD has slots for. This
is part of the DXIO/DDI descriptor handling cleanup.

BUG=b:158695393

Change-Id: Ia220d5a9d4ff11707b795b04662ff7eead4e2888
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43435
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 20:29:23 +00:00
Felix Held 8ced938763 vc/amd/fsp/picasso: update UPD header
A new version of UPD headers generated from the FSP tree. This adds UPDs
for downcoring and increases the number of DXIO descriptor slots.

BUG=b:161152720
TEST=SATA on Mandolin works now.

Cq-Depend: chrome-internal:3175393

Change-Id: I1e27597e22af4df65d206a38b67c4920298b30b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43659
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 20:29:11 +00:00
Maxim Polyakov 4eed5e9057 mb/ocp/tiogapass: Use macro to configure IIO
Use macros to configure each of the IIO ports instead of an array
of some unknown parameters. This will clean up the code and make
it easier to read.

Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical.

Change-Id: I2911992435a6c93624525426d56212f821abb866
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 14:36:42 +00:00
Angel Pons 8be5b59a41 nb/intel/sandybridge: Remove unnecessary `struct sys_info`
It was only used in one function, but its value was never read. Drop it.

Change-Id: Ib511352d51d4452d666640d0f52810b06c8d61ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24 14:30:03 +00:00
Angel Pons e4c0555230 nb/intel/ironlake: Move southbridge code to ibexpeak
There's no need to set up the southbridge in the northbridge code.

Change-Id: I0f80c92aca885812c27a8803c2745844d8dfb939
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24 14:29:36 +00:00
Angel Pons 1e1515fc9d sb/intel/*: Delete invalid comment
Looks like these comments were moved without checking them. They are no
longer correct nor useful, so kill them with fire.

Change-Id: I3de04b8c03f7c511376dec922a60958ffc3bf6a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24 14:28:33 +00:00
Jingle Hsu 1ba6201518 mb/ocp/deltalake: Send OEM IPMI command for CMOS clear on RTC failure
When RTC failure is detected, send IPMI OEM command to issue CMOS clear.
This is to let the payload (LinuxBoot) handle the IPMI OEM CMOS
clear command by resetting RTC data, erasing RW_VPD (TODO) and add a
SEL, then reboot the system.

Tested=on OCP Delta Lake, after removing RTC battery we can see the above
flow can be executed correctly.

Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43005
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 09:48:34 +00:00
Johnny Lin f9e12e82f7 mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU
2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting
   PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.

Tested on OCP Tioga Pass.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24 09:46:10 +00:00
Tony Huang 46c2d91a79 mb/google/octopus/variants/garg: update Garfour SKU ID
SKUID
51 - Garfour EVT (non-touch, TypeA DB)
52 - Garfour DVT (touch, HDMI DB)

BUG=b:161554087
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage

Change-Id: I3cb17c2b665c303da210817a531c869c6324b249
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Henry Sun <henrysun@google.com>
2020-07-24 07:00:55 +00:00
Raul E Rangel 728c0787f2 mb/google/zork: Don't expose reset GPIO for touchscreen to OS
The Raydium ACPI entry currently provides a reset GPIO and an _ON/_OFF
method to the kernel. These are contradictory. The ownership of the GPIO
should be mutually exclusive between either the OS or the FW. Since we
have two methods exposed this causes the OS to reset the TS twice. Once
using the _ON method, and once using the GPIO. Additionally the _ON
method is waiting for 20ms after reset while the OS driver uses a 50ms
delay. The Raydium TS datasheet specifies 20ms for FW ready time, so the
OS driver is adding additional padding.

The reference design has a 32ms rise time on the reset line. So without
this patch, the OS tries to reset the TS using the _ON method and it
waits for 20ms. This is not enough time for the reset line to reach
high, let alone account for the FW ready time. The OS driver then tries
to reset the device by toggling the GPIO. It waits 50ms which is still
2ms less than required.

This CL removes the GPIO from being exported in the _CRS so the OS
driver won't try and reset the device. It also increases the reset delay
by 32ms to account for the rise time.

This isn't a complete fix. I think that the slow rise time is causing
some kind of metastability in the TS reset hardware. Using a script to
bind and unbind the TS driver, the TS device becomes unresponsive after
~200 iterations. The only way to reset the device is to power cycle.

The TS power is also not currently controlled by the power resource.
This means that we have no guarantee over when the reset line is
toggled. This will lead to issues while spending and resuming.

BUG=b:160854397
TEST=Boot trembyle and make sure TS works. Suspend/Resume trembyle 300+
times.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-23 21:26:14 +00:00
Eric Peers be2d6541b9 mb/google/zork/variants/dalboz: Use HS200 for eMMC
Earlier versions of Dalboz did not correctly handle HS400. One fix was
to add stitching vias, but these boards did not have them. b/156539551

Another possible fix is to add tuning parameters including drive
strength, but that is still a WIP. b/158959725

This should correct OS load failures in the meantime by running the bus
slower.

BUG=b:158845662
TEST=build, flash, boot sku 0x5a80000c to OS
BRANCH=None
Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: Ia3e7a641bde04c5a7be29bf91c38dd8c110ed17a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43572
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 21:13:34 +00:00
Kevin Chiu 77b89c8b18 zork: Create dirinboz variant
Create the dirinboz variant of the dalboz reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:161579679
BRANCH=master
TEST=util/abuild/abuild -p none -t google/zork -x -a
make sure the build includes GOOGLE_DIRINBOZ

Change-Id: I33c03080ffbe0bca61acf4144417b9f5fff6389f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-07-23 17:56:52 +00:00
Mark Hsieh e00db59c7c mb/google/arcada: Enable bayhub 720 on Arcada
Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.

BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from SATA/PCIe-eMMC storage successfully

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43669
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 17:06:14 +00:00
Ivy Jian 311ddbd193 mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien.

BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from storage successfully

Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-07-23 17:05:38 +00:00
Karthikeyan Ramasubramanian d54c9b0fef mb/google/dedede/var/waddledoo: Configure stop delay for SiS TS
Reset the Touchscreen (TS) and disable the stop GPIO (report switch) at
the same time. Add a delay of 100 ms after disabling the stop GPIO. This
will ensure the required delay is inserted for both reset and stop
disable GPIOs simultaneously.

BUG=b:152936541
TEST=Build and boot the waddledoo mainboard. Ensure that the SiS
Touchscreen is functional.

Change-Id: Icbfb5e07a28ab72b1ff696ad1183a6c2173dcaac
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 15:50:55 +00:00
Karthikeyan Ramasubramanian d90616278c mb/google/dedede/var/drawcia: Generate SPD ID for supported parts
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR

BUG=None
TEST=Build the drawcia board.

Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 15:30:51 +00:00
Furquan Shaikh dcee4b6fa9 mb/google/zork: Fix Goodix touchscreen ACPI node
This change does the following:
a. USI_REPORT_EN is no longer set to high in coreboot. Instead
GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this
pad as required.
b. Appropriate delays are added for power-down sequencing:
 - Delay after REPORT_EN is disabled - 1ms
 - Delay after RESET is asserted - 1ms

BUG=b:159501288

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If4d12fa0d4f4e5123d8fdccdabda996dcafa4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23 14:11:49 +00:00
Furquan Shaikh 2978502705 mb/google/zork/var/morphius: Change hid and desc for Goodix touchscreen
Morphius uses Goodix touchscreen and not G2 touchscreen. This change
updates hid and desc properties in devicetree accordingly.

BUG=b:159501288

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I2527fa5409bb127ac225c6fb2a5f1bc24895f6cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23 14:11:39 +00:00