Current flash layout doesn't support the fsp debug builds since
the FW_MAIN_A/B doesn't have enough space to hold the fsp debug
binaries along with ME RW binaries.
This patch reduces the SI_ALL size to 3.5MiB and increase the
SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries.
BRANCH=dedede
TEST=Build and Boot jslrvp with fsp debug enabled coreboot.
Cq-Depend: chrome-internal:3425366
Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch modifies flash layout to add ME_RW_A/B to add
the CSE RW blob and also enable the CSE RW update feature for
JSLRVP
BUG=b:169077783
TEST= Built for jslrvp. Verified that CSE RW and metadata files
are included in cbfs.
Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.). As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache. The conditions are as follows:
1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
switch is true)
2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
means that memory training will occur after verified boot,
meaning that mrc_cache will be filled with data from executing
RW code. So in this case, we never want to use the training
data in the mrc_cache for recovery mode.
3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
means that memory training happens before verfied boot, meaning
that the mrc_cache data is generated by RO code, so it is safe
to use for a recovery boot.
4. Any platform that does not use vboot should be unaffected.
Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode. If the platform:
1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set
BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
ensure that memory retraining happens both times
run dut-control power_state:rec twice on lazor
ensure that memory retraining happens only first time
2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
boot twice to ensure caching of memory training occurred
on each boot.
Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update Power Limit2 (PL2) minimum value to the same as maximum value for
jasperlake rvp board. DTT does not throttle PL2, so this minimum value
change here does not impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on jasperlake rvp board
Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Refer to commit d7b88dc (mb/google/x86-boards: Get rid of power button
device in coreboot)
This change gets rid of the generic hardware power button from all
intel mainboards and relies completely on the fixed hardware power
button.
Change-Id: I8f9d73048041d42d809750fdb52092f40ab8f11f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change allows treating the PMC as a 'hidden' PCI device on
JasperLake, so that the MMIO & I/O resources can be exposed as
belonging to this device, instead of the system agent and LPC/eSPI.
Original patch for jasperlake SoC here:
CB:42018
This change was missing for JasperLake rvp board.
TEST=Checked PMC init function is called and also checked PCI resource
for PMC device 1f.2.
Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is
used for, so rename it to HAVE_SPD_BIN_IN_CBFS.
Change-Id: I4004c48da205949e05101039abd4cf32666787df
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add DTT (Dynamic Tuning Technology) support for Jasper Lake based rvp board.
Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None
BUG=Noe
TEST=Build and boot on jslrvp board
Change-Id: I41409c70d8472c54ca452fc98d5ee9edf3ccd307
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Drop duplicated code for spd.bin generation that is provided globally
in lib/Makefile.inc.
For all affected boards it has been verified that the output binary
functionally matches the original one. The changed execution order of
Make instructions influenced the cbfs file order. Hence, the rom images
can't be compared directly.
Thus, the output files of the two timeless abuild runs have been compared.
Further, it was verified that the final files in cbfs stay identical, by
comparing the extracted cbfs of each board.
The boards (possibly) needing modification could be found with something
like this (with false positives, though):
find src/mainboard -name Makefile.inc | \
xargs egrep 'SPD_BIN|SPD_DEPS' | cut -d: -f1 | sort -u
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Includes changes related to GPIO pad to configure I2C4 required for UFC
Change-Id: Ica3ac31f10214b8aff3bb64a2c3b42ccfa28bdcd
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Jasper Lake SoC had PCI root port mapping swap, thats why we were
using swapped mapping earlier for all the boards
Recently, patch was pushed to handle this swap in PCI enumeration code
for Jasper Lake and we need to correct this mapping. Now this mapping
aligns with actual port mapping in the schematics
BUG=None
BRANCH=None
TEST=NVMe and WLAN are getting detected after this changes
Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
More space is required in the COREBOOT CBFS to accommodate some features.
Currently no alternate firmware is stuffed into RW_LEGACY CBFS and has
~1 MB of unused space. Borrow some space from RW_LEGACY CBFS and extend
the RO_SECTION. Even within RO_SECTION, GBB requires only 12 KiB. So
adjust the GBB region accordingly and extend the COREBOOT CBFS.
BUG=b:162159386
TEST=Build the JSLRVP mainboard.
Change-Id: Ia8bb381c31ddf76f3211f9d4ac5c8c18c27834b7
Signed-off-by: Karthikeyan Ramasubramanain <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
reset on JSLRVP.
Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This change updates devicetree to enable SSDT generation for world
facing and user facing cameras of jasperlake_rvp. Also removes DSDT
changes related to the world facing camera.
Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch enables the SkipCpuReplacementCheck config for jasperlake rvp
to avoid the forced MRC training with the soldered down SOC.
BUG=b:160201335
BRANCH=None
TEST=Build and verify on jasperlake rvp with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530
Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
1. Configure GPIOs as per schematics
2. Add 1 Ports and 1 Endpoints
3. Add support for OTVI5675
WFC is on I2C5 with VCM support and using 2 data-lanes
BUG=None
BRANCH=None
TEST=Build and Boot jslrvp board and able to capture image
using world facing camera.
Change-Id: I07ae9e3473c16bde8eb1597460e70cc478357b98
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMI handler was not present in jasperlake rvp to handle wake events
when platform goes to sleep or shutdown or s0ix.
Adding this support for board which supports chromeec.
BUG=None
BRANCH=None
TEST=Check wake event on board and platform wakes up due to events
lid wake event or power button press.
Change-Id: I8e35955b06d6efaf9275ec03f519c9bcaa9ba345
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This patch configures all IP related GPIOs as per mainboard schematics.
Till now, we were relying on FSP to do IP specific GPIO programming but
now we'll program all GPIOs from mainboard.
This will remove ambiguity of GPIO programming done by FSP and coreboot
will do full GPIO programming
Programming GPIOs of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD
BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IP functionality working.
Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This CL selects the PcieRpClkReqDetect for the required root ports
which is needed to allow proper clksrc gpio configuration.
Also, sets the unused PcieClkSrcUsage to 0xFF.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
We need to configure GSPI related gpios for external EC and TPM.
Along with GSPI configuring gpios for LAN (power down), FSP_INT
and PCH_INT.
BUG=None
BRANCH=None
TEST=External EC card works and LAN is powered down.
Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1)Change Mainboard Part Number to jslrvp
2)Change Mainboard Family to Intel_jslrvp
3)Generate SMBIOS table and fill sku id information in SMBIOS
BUG=None
BRANCH=None
TEST=Mosys works on jslrvp and Sku ID info is generated
Change-Id: Iad0b394fea017223a5b98fff0cb4c2bd1d5a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40011
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Wifi and Bluetooth for Jasper Lake RVP with following changes:
1. Enable related pci root ports for WLAN and BT
2. Disable unused root ports and clkreq for unused clocks
3. Configure GPIOs properly for M.2 port
BUG=None
BRANCH=None
TEST=Code compiles and able to detect Wifi/BT module on board.
Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
M.2 WWAN interface has GPIOs which requires coreboot to
configure all related GPIOs as per board schematics.
BUG=None
BRANCH=None
TEST=code compiles and WWAN device is detected in OS
Change-Id: I8ad978a619b50e16ad754177f1eb05cf7670b79f
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Remove extra USB port entry because it came in from copy
patch from the previous board and configure USB over-current
pins as per JSLRVP.
Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
