Commit Graph

23234 Commits

Author SHA1 Message Date
Marc Jones 9ab8ae6a55 util/gitconfig: Make gitconfig a bash script
The gitconfig target has a few bashisms and would fail
silently on systems that use a POSIX standard sh (like Ubuntu dash).

Remove the code from the makefile and put it in a bash script that
is called by the gitconfig target.

Change-Id: I3bc8cf688a3ad211b57c8ca0e6b1e86c82dc6a37
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-12-15 23:02:11 +00:00
Kevin Chiu ea0aa33ea3 mb/google/snappy: add reset pin for Melfas touch controller
Melfas kernel TS driver (melfas_mip4.c) will look up "ce"
GPIO during driver probe in ACPI _DSD.
But FW does not report "ce-gpios" but "enable-gpios" in _DSD.
Kernel will obtain GPIO from _CRS by index "0" without ID.

Melfas driver does not have separate condition
for MIT-410 so driver will set TS IC power off in probe.

FW now may need to add back "reset" pin in order to hack
this condition to let Melfas driver get "useless" GPIO
so TS IC power (VTSP) will be not off during driver probe by itself.

BUG=b:70149336
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: Icf0451ff0c3df97cb2474e30542a2f46ba67d82a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-15 16:11:38 +00:00
Kane Chen 91ea9f0b90 mb/google/fizz: set SataMode to AHCI mode
For Fizz, the default should be AHCI mode and not RAID
mode. Additionally, there is only one drive connector, so
attaching several drives for a RAID is hard.

BUG=b:70146894

Change-Id: I2a9aa2d6281a916c00ff4659a927f164ba0e0705
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22837
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-15 06:43:34 +00:00
Marshall Dawson 0cc28d7e61 soc/intel/apollolake: Remove duplicate selects
Remove Kconfig selected symbols that are duplicates in the same file.

Change-Id: I21a3814131f0c8e08732e826dd1bcbb677cbe0aa
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22852
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-15 03:32:04 +00:00
Richard Spiegel 138a1d2a68 soc/amd/common: Update agesawrapper_call.h
Solve issues related to agesawrapper_call.h that came up at review
75dd50e233 (review 19724). This includes a hard coded table size and
2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER().

Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with
the actual content of the macro.

BUG=b:62240989
TEST=Build kahlee with no errors, boot recording serial output and compare
to serial output from a build without these changes.

Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-15 01:52:04 +00:00
Duncan Laurie 14485efbb3 soc/intel/skylake: Add integrated LAN config parameters
Add parameters to configure the integrated LAN via FSP.  Since
this takes over a PCI CLKREQ# pin it needs to know which pin
it should use, and there are additional parameters for LTR and
a "K1 power save" feature.

This was tested on a KBL-R board with integrated LAN, verifying
that the device is functional under Linux with the e1000e driver.

Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22856
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14 22:51:19 +00:00
Duncan Laurie 6827cb3857 drivers/spi: Enable flashconsole in verstage
Enable the flashconsole driver in verstage so it can be used
with VBOOT enabled.  This was tested on a VBOOT enabled system
using flashconsole to store the boot log.

Change-Id: Icd8a82dc962ece85b9fb3d2f5654369e821922eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14 22:51:12 +00:00
Duncan Laurie 466d8ce18e drivers/pc80/tpm: Remove unused ACPI opregion
The opregion and fields are left over from when ACPI ASL code was
reading registers to determine the current setup.  Now that the
ACPI device is generated with the correct information already this
code is not used at all and can be removed from the tree.

Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22854
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-14 22:51:05 +00:00
Patrick Georgi 0019f1a6c0 soc/intel/apollolake: add _RMV attributes to eMMC device ACPI
Required so Windows knows if the storage is removable or not.

Change-Id: I0822d767ada872d55357ff229e47e08fbe778a36
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/22830
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14 22:16:13 +00:00
Aaron Durbin 8240a88c05 soc/intel/common/block/i2c: fix orphaned Kconfig options
The SOC_INTEL_COMMON_LPSS_I2C option is no longer used. Likewise, the
SOC_INTEL_COMMON_LPSS_I2C_DEBUG option which is dependent on
SOC_INTEL_COMMON_LPSS_I2C is by definition not used either. Therefore,
remove SOC_INTEL_COMMON_LPSS_I2C and change the name/dependency
for SOC_INTEL_COMMON_LPSS_I2C_DEBUG to SOC_INTEL_COMMON_BLOCK_I2C_DEBUG.

BUG=b:70232394

Change-Id: Icd77f028b77d8f642690a50be4ac2c50d9ef511a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22874
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
2017-12-14 20:44:31 +00:00
Pratik Prajapati 73f073d393 mainboard/intel/glkrvp: Configure Prmrr and Enable SGX
Configure PRMRR to allocate 128MiB for SGX enclave memory and enable SGX
by default for GLKRVP platform.

Supported PRMRR size options:
0x02000000 - 32MiB
0x04000000 - 64MiB
0x08000000 - 128MiB

Change-Id: Ifa39df4a1da84bae49551a9626257bda0729752b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-14 20:12:50 +00:00
Pratik Prajapati ff3162b5e4 src/soc/intel/apollolake: include helpers.h in chip.h
include helpers.h in chip.h so that devicetree can use macros from helpers.h

Change-Id: Idfdee637a9b66a30be31b9ed113e1a44e4032f34
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/22774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-14 20:12:47 +00:00
Subrata Banik 73ff712082 soc/intel/cannonlake: Fix UART2 serial log broken issue
Cannonlake rvp serial log has been regressed with commit
I7eea910e065242689e87adac41281131674b39af(soc/intel/cannonlake:
Clean up UART code) because of common UART code is unable to
link all __weak function implementation from SoC uart.c due
to existing macro #define __SIMPLE_DEVICE__. Hence UART2 PCI
device resource programming is different than what it's been programmed
before.

This patch ensures UART2 PCI device resource enumeration is
working and we are getting serial log as expected.

Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14 18:39:01 +00:00
Martin Roth 96b2de9303 mainboard/google/kahlee: Update overcurrent pins
The overcurrent pins on kahlee weren't mapped correctly, causing
the USB-A port to stop working.

None of the EHCI only ports are used for external connectors, so all
of the overcurrent pins should go to the XHCI connections.  This is
also true of the Grunt board.

On Grunt, this also means that we don't need OC3, as it doesn't map
to anything in the XHCI controller, as it's coming from an internal
hub.

BUG=b:70636233
TEST=Build & boot Kahlee, verify USB-A port is working again.

Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2017-12-14 18:05:34 +00:00
Shaunak Saha ced08642eb mb/glkrvp: Enable Touchpad
This patch enables the APLS touchpad in glkrvp platform.

TEST= Boot and test touchpad works.

Change-Id: I6f52f7db57ab52b5531e647bde2adbb78b40f76f
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22627
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-14 17:33:45 +00:00
Richard Spiegel e89d444043 soc/amd/stoneyridge: Remove "\t" from name table
Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array
irq_association[], and change the print string in soc/amd/common/amd_pci_util.c
that use the names from "%s" to "%-20s". This sets a fixed field of 20
characters for the string name, allowing for variable length to the names
(up to 20 characters), thus saving memory space used by the strings.

BUG=b:70344551
TEST=Build and boot, record output of irq routing and verify alignment.

Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-14 03:51:03 +00:00
Bora Guvendik 1b75994b4e src/soc/intel/cannonlake: Add _PRW for CNVi
Add _PRW so that wake on WLAN feature works.

TEST=Boot to OS and check if WLAN device wakes host.

Change-Id: Id6689754d1c4100615e4e4ae5a7f9846f4bf785f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-12-13 20:56:25 +00:00
Shaunak Saha 562b168a77 mb/cannonlake_rvp: Enable Touchpad
This patch enables the APLS touchpad in cnl-y platform.

TEST= Boot and test touchpad works.

Change-Id: I461b9d119b1cac6c8c6cb9b096697f58e00d80ad
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22369
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-13 19:25:40 +00:00
Aaron Durbin 02b43aa2e0 vc/amd/pi/0067F00: add option to add AGESA binary PI as stage
Stage addition to CBFS allows relocation to happen on the fly. Take
advantage of that by adding AGESA binary PI as a stage file so that
each instance will be relocated properly within CBFS. Without this
patch Chrome OS having multiple CBFS instances just redirects the
AGESA calls back into RO which is inappropriate.

BUG=b:65442265,b:68141063
TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and
     noted each instance in Chrome OS build was relocated.

Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-13 15:53:24 +00:00
marxwang ec5a947b44 soc/intel/skylake: make tcc_offset take effect
Currently, "tcc_offset" defined in devicetree is overwritten by
Intel FSP-S UPD "TccActivationOffset".

This patch will make "TccActivationOffset" refer to "tcc_offset".

TEST=check if MSR (0x1a2[29:24]) value is updated with "tcc_offset"
     by iotools (rdmsr 0 0x1a2).

Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702
Signed-off-by: marxwang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/22818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-13 15:42:28 +00:00
Subrata Banik 1156c6656a soc/intel/apollolake: Remove set_subsystem() from SoC
Intel common PCI driver is handle PCI subsystem ID
programming, hence no need to have an explicit soc
function to do the same.

TEST=PCI subsystem id is getting programming during
pci enumeration.

Change-Id: I3eb362ff1f3f6d5c81a0dbe854d8ecd59d5a0453
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-13 10:20:41 +00:00
Subrata Banik 5c619a285c soc/intel/skylake: Remove set_subsystem() from SoC
Intel common PCI driver is handle PCI subsystem ID
programming, hence no need to have an explicit soc
function to do the same.

TEST=PCI subsystem id is getting programming during
pci enumeration.

Change-Id: Iead57a286b26d532e578cfff99f412c23fd4c2fe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-13 10:20:37 +00:00
Subrata Banik 6bbc91a964 soc/intel/common/block: Add option to have subsystem_id in common pci driver
This patch ensures all Intel common PCI devices can
have subsystem ID programmed along with PCI resource
enabling (.enable_resources) as part of PCI enumeration
process.

TEST=Build and boot KBL/CNL/APL/GLK to ensure PCI
subsystem ID getting programmed.
Example:
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/590c
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 8086/591e

Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22768
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13 10:20:32 +00:00
Subrata Banik ffc790bc7f device: Make pci_dev_ops_pci structure global
This patch makes pci_dev_ops_pci structure global so that
caller can make use of this structure using extern.

Change-Id: I8de919aacccbc062475fb04f59ffb4957d3460b9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-13 10:20:27 +00:00
Furquan Shaikh 55fa54d0c0 mb/google/poppy/variants/nami: Disable native SD card controller
This change selects Kconfig option to disable native SD card
controller in ACPI tables, since it is not used on nami.

BUG=b:70160119

Change-Id: I6180c2b342c69e6a7c357f10b6297d67ea0211d7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13 05:24:17 +00:00
David Wu 0f82905be4 mb/google/fizz: Enable SATA on port 0
Enable SATA port 0 to support SATA HDD.

BUG=b:69950854
BRANCH=None
TEST=emerge-fizz coreboot and boot on fizz dut

Change-Id: Ifbf5950151758286f8bff7250a68d9d0b3975ef9
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13 03:57:01 +00:00
praveen hodagatta pranesh d6dffdc1fa soc/intel/skylake: Enable LPC IO Decoding on PCR
According to the PCH BIOS Spec (Doc#549921/Rev-2.3.4),
section 2.5.1.6, it is a requirement to program the same
value programmed in LPC "PCI offset 82h" into "PCR[DMI]+2774h"
to fully enable the Lpc IO enable decoding which is missing in
current source.

Without above changes, Skylake Saddlebrook platform with a
SIO does not boot.

Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173
Signed-off-by: praveen <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/22819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13 02:19:54 +00:00
Martin Roth ac9d6b8c73 util/cbmem: Print timestamp frequency in verbose mode
The code flow is changed slightly to print the timestamp frequency from
either method of determining it.

BUG=b:70432544
TEST=Build and test cbmem -t -V

Change-Id: I02286fa67919e70a3592cdbcc1c9ca2991b7f385
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12 22:27:05 +00:00
Marc Jones 8976e0dbe9 google/kahlee/grunt: Add SPD files
MEM_ID SPD
 0000  hynix-H5AN8G6NAFR-UHC
 0001  hynix-H5ANAG6NAMR-UHC
 0010  micron-MT40A51216JY-083E
 0011  micron-MT40A1G16KNR-075E
 0100  samsung-K4A8G165WB-BCRC
 0101  samsung-K4AAG165WB-MCRC

BUG=b:69268926
TEST=build test

Change-Id: I1fd6335b3f8842252c42009a0a91a5b6ed3ea238
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12 21:12:48 +00:00
Aaron Durbin 49ec3f0a5f vc/amd/pi/00670F00: fix #include paths to only use <amdblocks/header.h>
Ensure that soc/amd/common/blocks/include is the only #include
path for the AMD common code. This removes the duplicate soc/amd/common
include as well using the correct #include header in AGESA.c.

BUG=b:69262110

Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-12 20:31:06 +00:00
Lin Huang 318a03a417 google/scarlet: support INNOLUX P097PFG panel
Add INNOLUX P097PFG panel timing. According to Scalet schematic,
if GPIO3_D4 get low status, it will use INNOLUX P097PFG panel;
if GPIO3_D4 get high status, it will use KD097d04 panel.

Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12 19:13:22 +00:00
Richard Spiegel 19f67a392a soc/amd/common: Move AGESA related source files
Move AGESA related source files in soc/amd/common under block directory.
Folder soc/amd/common/block subfolders should mimic soc/intel/common/block
subfolders (one subfolder per subject).

BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).

Change-Id: I497cdefe64e8dff00aaff7153c4ffa9c57c9acf8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12 16:25:33 +00:00
Richard Spiegel 0ad74ace8b soc/amd/common: Move Agesa related headers
Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.

BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).

Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-12 16:24:38 +00:00
Arthur Heymans f6f4ba9e45 nb/intel/x4x/rcven.c: Fix programming coarse offset
This fixes some bitwise logic errors that caused the coarse offset not
to be programmed.

This fixes a regression introduced by 6d7a8c
"nb/intel/x4x/raminit: Rework receive enable calibration"
where the coarse offset doesn't get programmed anymore.

TESTED on Foxconn g41s-k on a DIMM where the final DQS receive enable
delays are close but above and below the edge of a coarse delay setting.

Change-Id: I41869815f782a2ea1178bdea006e3a7587441323
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12 12:05:22 +00:00
Arthur Heymans cda1c4a521 mb/lenovo/t400/blc.c: Add a new panel to the list
Also adds a comment in the code to clarify what this array is about.

Change-Id: I04b185a5dbd7a7ccb039820f19d2cb549b9a2eac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-12 12:05:14 +00:00
Nico Huber 82049cb850 drivers/intel/gma: Power up legacy VGA block early
This is required at least on Skylake to be able to configure text mode.
3rdparty/libgfxinit is also updated by the single commit:

    42fb2d065d gma: Add procedure to power up legacy VGA block

Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-12 09:20:07 +00:00
Furquan Shaikh 060e2eb4f0 mb/google/poppy/variants/nami: Implement variant_memory_params
This change provides implementation of variant_memory_params for
nami. Since it uses DDR4 memory, DQ-DQS mapping table is not
required. Also, Rcomp resistor values are provided based on SDP v/s
DDP memory.

BUG=b:70188937

Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-12 05:17:45 +00:00
Furquan Shaikh d46e216d00 mb/google/poppy/variants/soraka: Tune I2C5 params
This change updates scl_lcnt value for I2C5 to bring the bus frequency
closer to 400kHz.

BUG=b:65062416
TEST=Verified that I2C5 frequency is between 389-396kHz.

Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11 21:09:46 +00:00
Richard Spiegel 2bbc3dc28d soc/amd/common: Move files to common/block
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit.

BUG=b:62240201
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).

Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11 20:26:26 +00:00
Lijian Zhao 408d76f867 soc/intel/cannonlake: Add support for D0 stepping
D0 stepping with CPUID 0x60663 need to be added in coreboot.

TEST=Boot up with D0 stepping processor

Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11 19:29:15 +00:00
Julius Werner 5598db254f google/gru: Stop mucking with unused I2S0 pins in codec config
Due to a schematic error, our code was written to configure more I2S0
pins than are actually used. We're also pinmuxing the whole bank of pins
over to the I2S controller even though we don't need them all. Restrict
the GPIO initialization and pinmuxing to the pins we really need so the
other ones can be correctly used as SKU ID pins on Scarlet.

Also, move the "audio" IO voltage domain selection to the other such
selections in the bootblock, since that covers two whole banks of GPIOs
and there's no guarantee that they're all used for audio (and thus not
needed before ramstage).

BUG=b:69373077
TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2.

Change-Id: I9314617e725fe83d254984529f269d4442e736f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-12-11 19:03:45 +00:00
Julius Werner ef935f04e0 google/gru: Change Scarlet SKU ID pins to pull-ups
These pins need to be pull-ups. I forgot.

BUG=b:69373077

Change-Id: I9314617e01d35898254984529f269d4442e736f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-11 19:03:33 +00:00
Martin Roth 888c9f6097 mainboard/purism/librem_skl: Fix line length > 80 characters
Make lint-stable was giving an error on this.

Change-Id: I06d11d86151f683b82b6df537e3de8c52d33e8b4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-12-11 18:54:58 +00:00
Martin Roth bc5c3e75a4 soc/amd/common: Collect timestamps before and after AGESA calls
BUG=b:70432544
TEST=Build & boot kahlee. Look at timestamps.

Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-11 17:31:42 +00:00
Martin Roth fbfe654c06 commonlib: Add timestamp codes for AGESA
BUG=b:70432544
TEST=Build & boot kahlee. Look at timestamps.

Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11 17:31:38 +00:00
Naveen Manohar 1533dfdd0e google/nautilus: Add Maxim98357a support
Adds Maxim98357a support for Nautilus using the generic driver
in drivers/generic/max98357

BUG=b:68686020
TEST=With entire merged audio should be enabled on max98357
speaker codec.

Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-11 14:25:59 +00:00
Naveen Manohar 3417ee9a3f mb/google/poppy/variants/nautilus: add SPK DMIC nhlt support
Nautilus board uses max989357a speaker codec and 4CH DMIC.
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.

BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on Speaker and captures on 4CH DMIC

Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-11 14:25:08 +00:00
Arthur Heymans 6d1fdb3410 AMD fam10: Link southbridge/amd/rs780/early_setup.c
Removes rs780_before_pci_init() since it was a no-op anyway.

Removes get_nb_rev() since this function is provided via a macro in
the header.

This Makes a lot of function non-static since the header has
prototypes for these.

Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-11 11:58:02 +00:00
Elyes HAOUAS f6bbc603fa intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c
Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11 01:10:51 +00:00
Aaron Durbin a78319ba26 vc/amd/pi/00670F00/binaryPI: cache the AGESA dispatcher
Instead of repeatedly walking cbfs for the AGESA blob and parsing it
cache the resulting dispatcher value. There's only one dispatcher table
so use it. The resulting change is that this work is done one time per
stage.

BUG=b:70401101
TEST=Booted and noted only one lookup per stage.

Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2017-12-11 01:07:31 +00:00