Commit Graph

18062 Commits

Author SHA1 Message Date
Aaron Durbin 28a4e0e460 commonlib: fix 'AFTER CAR' spacing to align with others
The cbmem string for 'AFTER CAR' didn't have the proper spacing
so when that entry is added to cbmem it results in a misaligned
log entry with the others.

Change-Id: If940e85b7dc5fb8372d7e2845270dadad67ab3a0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15735
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19 20:13:38 +02:00
Aaron Durbin 5fbe12dc7e lib: provide memrange library in romstage
BUG=chrome-os-partner:52679

Change-Id: I79ffc0749fba353cd959df727fb45ca2ee5c1bf6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15734
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19 20:13:20 +02:00
Aaron Durbin 746b906cf9 mainboard/google/reef: explicitly set shipping Chrome OS options
The Chrome OS options that will be shipped on this platform were
being set in the chromium repo with an external config file. Set
the options in the mainboard Kconfig file so there's no discrepancy
as to what will be used.

Change-Id: I05f0d1245611c16f54273728519a08e6edff3429
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15733
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19 20:13:08 +02:00
Andrey Petrov dc97b1ce2f soc/intel/apollolake: Fix bitshift issue in bootblock
Fix issue where zero-sized BIOS region could cause bitshift
for '-1' which is an unspecified behavior.

Change-Id: Icb62bf413a1a0d293657503ef21fe97b5f9a5484
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15727
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19 18:57:13 +02:00
Damien Zammit b921725b52 nb/intel/x4x: Fix CAS latency detection
Fix and use the failsafe CAS detection logic rather than
recalulating the values from raw SPDs.

Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs
(which worked before and still work)

Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15726
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-07-19 18:55:50 +02:00
Jonathan Neuschäfer 47995fbb36 arch/riscv: Remove enter_supervisor
This function is unused since coreboot starts payloads in machine mode,
and it uses the obsolete eret instruction.

Change-Id: I98d7d0de5a3959821c21a0ba4319efb610fdefde
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15729
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-18 22:51:13 +02:00
Jonathan Neuschäfer b8e67acc91 arch/riscv: Change all eret instructions to .word 0x30200073 (mret)
Using the opcode directly is necessary for the transition to the GCC
6.1.0 based toolchain, because the old toolchain only supports eret and
the new toolchain only supports mret.

Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15290
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-18 22:50:33 +02:00
YH Huang 5d687add85 google/oak & elm: initialize touchscreen reset gpio
In order to save power in S3, we remove reset gpio setting in kernel.
We still need to initialize touchscreen ic.
Do it by pulling low reset gpio for 500us and then pulling high
in firmware.

BRANCH=none
BUG=chrome-os-partner:55170
TEST=build on elm.

Change-Id: Idbe0175a1fc1fa0b05e81706194c79d52c6101f6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: f40cc9a22c2551c2c9455cb8b60f36353602bca6
Original-Change-Id: If2ac815c4fd5c5ae15443348a49eb31449b724b1
Original-Signed-off-by: YH Huang <yh.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360312
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Reviewed-on: https://review.coreboot.org/15719
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-18 20:14:29 +02:00
Vadim Bendebury b4d3d09ded gru: implement hw reset function
Asserting this GPIO will send a signal to the EC to trigger a reset
for the AP and the CR50.

BRANCH=none
BUG=chrome-os-partner:55252
TEST=the device now reboots when it needs to switch between different
     boot modes instead of hanging with "failed to reboot" message.

Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7
Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/360238
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15718
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-18 20:14:07 +02:00
Furquan Shaikh e19d9af9ee elog: Use rdev_mmap to find offset of ELOG
In case of elog not being stored in CBMEM, calculate flash offset by
using rdev_mmap instead of assuming that the entire flash is mapped just
below 4GiB. This allows custom mappings of flash to correctly convert
the flash offset to mmap address.

BUG=chrome-os-partner:54186
TEST=Verified behavior on reef. mosys able to read out the elog correctly.

Change-Id: I3eacd2c9266ecc3da1bd45c86ff9d0e8153ca3f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15722
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-18 08:12:12 +02:00
Andrey Korolyov d83b0e9ac4 mainboard/amd: add support for F2950 system board
F2950 SBC, also known as TONK 1201/TONK 1202, was originally
produced as a Centerm F2950 using DB800 reference design. Common
configuration does include a 600 MHz GeodeLX CPU underclocked to
500 or 400 MHz, 128 or 512 MiB of RAM in the single SODIMM slot and
128 or 512 MB IDE DOM. The board does have three USB 2.0 ports
(none of them possessing debug capabilities), PS/2, VGA, Geode
audio in/out and the serial port.

EEPROM needs to be soldered out and flashed externally at the time
of this message because flashrom would neither be able to dump BIOS
correctly while running vendor BIOS nor write flash contents.

All peripherals were tested against Linux 3.16 and seem to work
flawlessly. At the moment of this commit coreboot does not pass
PCI_COMMAND_IO from the configuration space to SeaBIOS, thereby
preventing VGA OPROM from being executed. This would be fixed in
the SeaBIOS itself or in a subsequent commit. As a workaround,
user may put VGA OPROM to vgaroms/seavgabios.bin in CBFS.

Signed-off-by: Andrey Korolyov <andrey@xdel.ru>

Change-Id: I93f13ecb53bd05abc0e07e0bd7ba40e646dcb4c4
Reviewed-on: https://review.coreboot.org/15565
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-17 16:50:35 +02:00
Harsha Priya 3a96ac44e2 acpi: Change API called to write the name for ACPI_DP_TYPE_CHILD
The API called to write the name of the child table in the
dp entry (type ACPI_DP_TYPE_CHILD) was not including the
quotes, e.g., it was DAAD and not "DAAD". Thus, the kernel driver
did not get the right information from SSDT.

Change the API to acpigen_write_string() to fix the issue.

Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8984e7
Reviewed-on: https://review.coreboot.org/15724
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-17 02:26:13 +02:00
Martin Roth 6101dfbaf3 buildgcc: Update the revision to 1.41
The binutils patch went in without updating the revision,
so we need to update it now. This was done in commit bcfa7ccb
(buildgcc: Update to binutils-2.26.1 & Fix aarch64 build issue)

Change-Id: Ifad4a2e3973f1f60d0ea840945e2bd097e1b4474
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15712
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-16 00:03:30 +02:00
Shaunak Saha 9b4be0fce0 intel/amenia: Add wake-up from lid open
This patch adds support to wake up from S3 on lidopen.
mainboard.asl has the _PRW defined for the wakeup support
in S3.

BUG = chrome-os-partner:53992
TEST = Platform wakes up from S3 on lidopen.

Change-Id: I48b456baf5f7e1c2f28454fa66bb90ad761bb103
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15618
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 21:02:20 +02:00
Andrey Petrov 89e7b49a11 soc/intel/apollolake: Consolidate ISH enabling
Since the Integrated Sensor Hub can be disabled through devicetree.cb
as a PCI device, there is no need for a separate register variable.
Remove handling the register and update mainboards' devicetrees. Also
keep ISH disabled on both Reef and Amenia.

Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15710
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 18:21:54 +02:00
Kane Chen d779605c29 soc/intel/apollolake: Properly disable PCIe root ports
1. The hotplug feature needs to be disabled
   so that pcie root ports will be disabled by fsp
2. Correct PcieRootPortEn mapping.
The correct mapping should be like below
PcieRootPortEn[0] ==>  00:14.0
PcieRootPortEn[1] ==>  00:14.1
PcieRootPortEn[2] ==>  00:13.0
PcieRootPortEn[3] ==>  00:13.1
PcieRootPortEn[4] ==>  00:13.2
PcieRootPortEn[5] ==>  00:13.3

BUG=chrome-os-partner:54288
BRANCH=None
TEST=Checked pcie root port is disabled properly
and make sure pcie ports are coalesced.
Also make sure the device will still be enabled after coalescence
when pcie on function 0 is disabled devicetree

Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/15595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 18:20:54 +02:00
Shaunak Saha 97fc426070 google/reef: Add wake-up from lid open
This patch adds support to wake up from S3 on lidopen.
mainboard.asl has the _PRW defined for the wakeup support
in S3.

BUG = chrome-os-partner:53992
TEST = Reef board wakes up from S3 on lidopen.

Change-Id: Ic3bae26cea0642f98d938b3523d08f5902a1f4b5
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 18:20:35 +02:00
Kyösti Mälkki df6eb79a22 intel/x4x: Do not use scratchpad register for ACPI S3
If S3 support was implemented for this platform later on, use
romstage handoff structure instead.

Change-Id: I03c1e07a7fcc17c27203d0c4e32e3958f2ba5273
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15716
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15 16:57:57 +02:00
Kyösti Mälkki 32a38ee85b intel/pineview: Do not use scratchpad register for ACPI S3
If S3 support was implemented for this platform later on, use
romstage handoff structure instead.

Change-Id: Ib0cf3ad41753baee26354c5ed19294048e7fb533
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15715
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15 16:57:46 +02:00
Kyösti Mälkki cbb23af2da AMD binaryPI: Use common romstage ram stack
Note that no binaryPI board has HAVE_ACPI_RESUME.

Change-Id: I52d0bd7dac86822242400f68f6dc202f02d6e0f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:31:07 +02:00
Kyösti Mälkki f32d5b8b66 AMD binaryPI: Split romstage ram stack
Change-Id: Ibbff1fdb1af247550815532ef12f078229f12321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15467
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:20:21 +02:00
Kyösti Mälkki bd274e1363 AMD binaryPI: Use common ACPI S3 recovery
Note that no binaryPI board has HAVE_ACPI_RESUME.

Change-Id: Ic7d87aa81c75374dd1570cef412a3ca245285d58
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15254
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:19:18 +02:00
Kyösti Mälkki bce9bbdfd4 AGESA: Use common romstage ram stack
Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:18:54 +02:00
Kyösti Mälkki a2a7e981d6 AGESA: Use common ACPI S3 recovery
Change-Id: I8ce91088c5fa1a2d2abc53b23e423939fe759117
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15253
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:18:30 +02:00
Aaron Durbin 3969df875e mainboards/skylake: use common Chrome EC SMI helpers
Reduce duplicate code by using the Chrome EC SMI helper functions.

BUG=chrome-os-partner:54977

Change-Id: Ie83e93db514aa0e12e71d371d7afab34a70797fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15689
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15 08:36:24 +02:00
Aaron Durbin 38613d079d soc/intel/skylake: provide poweroff() implementation
Implement poweroff() by putting the chipset into ACPI S5 state.

BUG=chrome-os-partner:54977

Change-Id: I9288dcee13347a8aa3f822ca3d75148ba2792859
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15688
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:36:12 +02:00
Aaron Durbin 1a75560599 mainboards/apollolake: use common Chrome EC SMI helpers
Reduce duplicate code by using the Chrome EC SMI helper functions.

BUG=chrome-os-partner:54977

Change-Id: Iba2ca7185ad7f0566858ce99f5ad8325ecc243cf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15687
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-07-15 08:35:59 +02:00
Aaron Durbin c2b7779d60 soc/intel/apollolake: provide poweroff() implementation
Implement poweroff() by putting the chipset into ACPI S5 state.

BUG=chrome-os-partner:54977

Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15686
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:35:49 +02:00
Aaron Durbin 996b15c934 ec/google/chromeec: provide common SMI handler helpers
The mainboards which use the Chrome EC duplicate the
same logic in the mainboard smi handler. Provide common
helper functions for those boards to utilize.

BUG=chrome-os-partner:54977

Change-Id: I0d3ad617d211ecbea302114b17ad700b935e24d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:35:29 +02:00
Aaron Durbin b743b1a843 lib: add poweroff() declaration
Add a function to power off the system within the halt.h header.

BUG=chrome-os-partner:54977

Change-Id: I21ca9de38d4ca67c77272031cc20f3f1d015f8fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:35:15 +02:00
Aaron Durbin f1e22d5c39 soc/intel/quark: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I034c083604892a5fa25dff3b50e327e0a885b021
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:34:58 +02:00
Aaron Durbin bf168e740f southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I884da90d24bc41e566a290f4135166d9e0cdf474
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15682
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:34:46 +02:00
Aaron Durbin 648c9ae371 southbridge/intel/fsp_i89xx: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ibf2bc3ae89cb5a013cb1ccc439c906b00bf78d66
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15681
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:34:35 +02:00
Aaron Durbin 4d7a9a5569 southbridge/intel/fsp_rangeley: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ia113672fa3cb740cb193c23fd06181d9ce895ac3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:34:22 +02:00
Aaron Durbin e99194555b southbridge/intel/i82801gx: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I08fb52ca13a4355d95fe31516c43de18d40de140
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15679
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:34:10 +02:00
Aaron Durbin 671909b891 southbridge/intel/i82801dx: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I29918fe70b5e511785ed920d8953de3281694be2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:53 +02:00
Aaron Durbin 78c6843a2b southbridge/intel/ibexpeak: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I65270ddcb612f9c63d7dbb2409e4395f96e10a51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15677
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:39 +02:00
Aaron Durbin da5f5094f0 southbridge/intel/lynxpoint: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I03051c1c1df3e64abeedd6370a440111ade59742
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15676
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:30 +02:00
Aaron Durbin 340898f21a southbridge/intel/bd82x6x: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ie709e5d232c474b41f2ea73d3785a7975d6604ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15675
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:18 +02:00
Aaron Durbin 15e439a72e soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:03 +02:00
Aaron Durbin 9e6d143a82 soc/intel/broadwell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:32:49 +02:00
Aaron Durbin c159bb0d76 soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Iecd94494cb568b20bdf6649b46a9a9586074bdc7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15672
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: York Yang <york.yang@intel.com>
2016-07-15 08:32:35 +02:00
Aaron Durbin e0a49147a6 soc/intel/skylake: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15671
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:32:22 +02:00
Aaron Durbin 1b6196dec9 soc/intel/braswell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:32:09 +02:00
Aaron Durbin f5cfaa3934 soc/intel/baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15669
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:31:56 +02:00
Aaron Durbin 56db47fe20 soc/intel/common: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I40560b2a65a0cff6808ccdec80e0339786bf8908
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15668
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:31:44 +02:00
Aaron Durbin ed35b7c546 soc/intel/apollolake: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15667
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-15 08:31:33 +02:00
Aaron Durbin 20a588b3de arch/x86: provide common Intel ACPI hardware definitions
In the ACPI specification the PM1 register locations are well
defined, but the sleep type values are hardware specific. That
said, the Intel chipsets have been consistent with the values
they use. Therefore, provide those hardware definitions as well
a helper function for translating the hardware values to the
more high level ACPI sleep values.

BUG=chrome-os-partner:54977

Change-Id: Iaeda082e362de5d440256d05e6885b3388ffbe43
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15666
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:31:21 +02:00
Aaron Durbin 932e09d168 drivers/intel/fsp1_1: align on using ACPI_Sx definitions
The SLEEP_STATE_x definitions in the chipsets utilizing
FSP 1.1. driver have the exact same values as the ACPI_Sx
definitions. The chipsets will be moved over subsequently,
but updating this first allows the per-chipset patches
to be isolated.

BUG=chrome-os-partner:54977

Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15665
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:31:09 +02:00
Aaron Durbin 9fe0ff2f83 mainboards: remove direct acpi_slp_type usage
Use the acpi_is_wakeup_s3() API instead of comparing
a raw value to a global variable. This allows for
easier refactoring.

Change-Id: I2813b5d275cbe700be713272e3a88fdb5759db99
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15690
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-07-15 08:30:53 +02:00