Commit Graph

52413 Commits

Author SHA1 Message Date
Sean Rhodes 2980e317e3 soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is only used on `starlabs/starbook` which
selects D3COLD_SUPPORT so the UPDs will not change.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20 20:43:29 +00:00
Sean Rhodes 648ff9268f soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep state
Use D3COLD_SUPPORT Kconfig option to set the maximum support sleep
state. Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as
if it is not, it will break S3 exit.

When D3COLD_SUPPORT is not enabled, return `3` (D3Hot).

This fixed S3 exit on both TGL and ADL. Tested on StarBook
Mk V and Mk VI.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I578d4933b6144aec79fe0b2eb168338ef82c0b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74406
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-20 20:43:02 +00:00
Sean Rhodes 5f0cda7e91 soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORT
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.

Remove it, and instead use D3COLD_SUPPORT so it's clear what the
option is doing.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20 20:42:41 +00:00
Sean Rhodes aa8c6a22e5 device: Move D3COLD_SUPPORT symbol
Move D3COLD_SUPPORT to device, so it can be used by multiple
SOCs.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie92736458ab95374c51346107665dc0fd1e653a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74404
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20 20:42:18 +00:00
Fred Reitberger 67bc6ab1e9 mb/amd/birman: Enable PCIe RTD3 support
Add PCIe RTD3 support so the NVMe gets placed into D3 when entering s0i3

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-20 12:45:48 +00:00
Fred Reitberger c706880bfe mb/amd/birman: Update DXIO descriptors per schematic
Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B
v0.7

Update devicetree to reference the updated DXIO descriptors.

TEST=boot birman and note the devices show up in the logs correctly

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-20 12:45:31 +00:00
Subrata Banik 03ff5db8b8 soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS
The Intel FSP used on ChromeOS platform has dropped the
`CpuFeaturesPei.ffs` module to opt for coreboot running this
additional feature programming on BSP and APs.

TEST=Able to build and boot google/rex without any boot regression.
Please refer to the boot time and SPI flash savings after dropping
the FSP feature programming:

Boot time savings=10ms
SPI Flash size savings=34KB

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-20 08:31:50 +00:00
Fred Reitberger 3c8a8c2eb0 mb/amd/birman/ec.c: Update EC configuration
Update the EC GPIO values for Birman, per schematic # 105-D67000-00B

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73971
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19 22:25:34 +00:00
Jon Murphy fb5d1573c3 mb/google/myst: Add initial fch irq routing
Add initial fch irq routing table for Myst.

BUG=b:275946702
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74109
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19 21:50:59 +00:00
Karthikeyan Ramasubramanian e4fd7dc9ff soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
CBFS library performs memory mapped access of the files during loading,
verification and de-compression. Even with MTRRs configured correctly,
first few file access through memory map are taking longer times to
load. Update the SPI DMA driver to load the files into CBFS cache, so
that they can be verified and de-compressed with less overhead. This
saves ~60 ms in boot time.

BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Observe ~60 ms improvement
with the boot time. Performing additional test to confirm there are no
regressions.
Before:
=======
 970:loading FSP-M
  15:starting LZMA decompress (ignore for x86)       760,906 (60,035)
  16:finished LZMA decompress (ignore for x86)       798,787 (37,881)
   8:starting to load ramstage
  17:starting LZ4 decompress (ignore for x86)        1,050,093 (13,790)
  18:finished LZ4 decompress (ignore for x86)        1,054,086 (3,993)
 971:loading FSP-S
  17:starting LZ4 decompress (ignore for x86)        1,067,778 (3,313)
  18:finished LZ4 decompress (ignore for x86)        1,068,022 (244)
  90:starting to load payload
  17:starting LZ4 decompress (ignore for x86)        1,302,155 (11,285)
  18:finished LZ4 decompress (ignore for x86)        1,303,938 (1,783)

After:
======
 970:loading FSP-M
  15:starting LZMA decompress (ignore for x86)       709,542 (12,178)
  16:finished LZMA decompress (ignore for x86)       739,379 (29,837)
   8:starting to load ramstage
  17:starting LZ4 decompress (ignore for x86)        1,001,316 (12,368)
  18:finished LZ4 decompress (ignore for x86)        1,001,971 (655)
 971:loading FSP-S
  17:starting LZ4 decompress (ignore for x86)        1,016,514 (3,031)
  18:finished LZ4 decompress (ignore for x86)        1,016,722 (207)
  90:starting to load payload
  17:starting LZ4 decompress (ignore for x86)        1,244,602 (10,313)
  18:finished LZ4 decompress (ignore for x86)        1,244,831 (228)

Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-04-19 19:09:47 +00:00
Jon Murphy ea68fa0b23 mb/google/skyrim: Fix eMMC reset GPIO
On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6).
Update the port_descriptors to link the correct reset GPIO. Data
is from the skyrim variant schematics and go/skyrim-gpios.

BUG=b:278759559
TEST=reboot: 5 iterations
suspend_stress_test: 10 iterations

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74512
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-19 19:09:11 +00:00
Terry Chen 15ad4b008a mb/google/brya/var/crota: select SOC_INTEL_RAPTORLAKE
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as crota is using a converged firmware image.

BUG=b:267249674
BRANCH=firmware-brya-14505.B
TEST="FW_NAME=crota emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage"

Cq-Depend: chromium:4430832
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I448c58f93fddc44904c1f5ef3f8939618eff536f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-19 15:30:50 +00:00
Sheng-Liang Pan df029ede73 mb/google/kukui: Add sdram configs for RAM code 0x33 and 0x34
Add sdram configs:
- RAM code 0x33: sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB SPD for
 K4UBE3D4AB-MGCL 4GB
- RAM code 0x34: sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB for
 H54G68CYRBX248 8GB

BUG=b:278644249
BRANCH=kukui
TEST=emerge-jacuzzi coreboot

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If5b484b5324ba39dbb220f12bdb8344ecb5c4da5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73469
Reviewed-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19 13:28:44 +00:00
Sean Rhodes 1d41f909f3 soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.

Rename it to D3COLD_SUPPORT to make it clear what it's doing.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-19 13:25:29 +00:00
Morris Hsu bf66d66593 mb/google/brya/var/constitution: Generate SPD ID for supported parts
Add supported memory part in mem_parts_used.txt, then generate.

K4UBE3D4AB-MGCL

BUG=b:267539938
TEST=run part_id_gen to generate SPD id

Change-Id: Iee41bb4511f2d77e5ddc2798f9d4db6137ed818d
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74497
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-19 09:27:21 +00:00
Anand Vaikar 03232e93d3 mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF),
hence update the correct bridge number in the device tree.

TEST: Builds and boots, the device enumerates.
[DEBUG]  PCI: 00:02.4 [1022/14ee] enabled
[DEBUG]  PCI: 01:00.0 [144d/a80a] enabled
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-18 15:16:37 +00:00
Sergii Dmytruk 28eaa4a340 src/cpu/power9: move part of scom.h to scom.c
Reset function, constants and include are not used outside of scom.c and
not going to be.

Change-Id: Iff4e98ae52c7099954f0c20fcb639eb87af15534
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-04-18 13:05:56 +00:00
Jamie Chen 60b22c4c57 mb/google/brya/var/omnigul: Adjust I2Cs CLK to be around 400 kHz
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.

Tuning i2c frequency for omnigul
I2C0 - Audio CLK : 293.7khz
I2C1 - TPM CLK : 388.8khz
I2C3 - Touch Screen CLK : 294.8khz
I2C5 - Touch Pad CLK : 389.2khz

BUG=b:275061994
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot, and measure i2c clock.

Change-Id: I7c4fdf0e003318a69b870b487a60accefbc0ffed
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-18 13:04:35 +00:00
Elyes Haouas b68817d196 crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3
Change-Id: Iab8d67632f97c596baa9b430228d4aae6fa48126
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-17 23:43:12 +00:00
Kyösti Mälkki d2a22e5fc0 Makefiles: Drop redundant VARIANT_DIR definitions
Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-17 13:47:28 +00:00
kevin3.yang 935c8ea952 mb/google/dedede/var/boten: Generate SPD ID for supported memory part
Add boten supported memory parts in mem_parts_used.txt, generate
SPD id for this part.

1. Samsung K4U6E3S4AB-MGCL

BUG=b:278138388
TEST=Use part_id_gen to generate related settings

Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I5f910393847c6494f77c009cb11f50b31bebffb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-17 13:45:03 +00:00
Anil Kumar e0e963e140 mb/google/rex: Enable all DDI lanes
This patch enables all DDI ports on Rex board to support display port
tunneling and dual display on TBT dock.

BUG=b:273901499
TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74413
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-17 13:44:43 +00:00
Kyösti Mälkki dc2285bc05 sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines
Change-Id: I242e05ee63f46bedbab3a425e922e60f1c749a15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-17 08:14:29 +00:00
Kyösti Mälkki d521b967c4 cpu,soc/intel: Separate single SSDT CPU entry
Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-17 08:13:38 +00:00
Tarun Tuli 15dd44eedd mb/google/brya/variants/hades: Update GPIO configs
Update GPIO configs based on latest schematics (revision aabe36)

Move GPP_D4->GPP_A13 (BT_DISABLE_L)
Swap GPP_E3<>GPP_E8 (WIFI_DISABLE_L and PG_PPVAR_GPU_NVVDD_X_OD)
Move GPP_A13->GPP_A20  (GSC_PCH_INT_ODL)

BUG=b:269371363
TEST=builds

Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-17 05:43:14 +00:00
Tyler Wang 7fd0c59969 mb/google/nissa/var/craask: Add GTCH7503 and split TS by SSFC
Add G2 touchscreen GTCH7503 for craaskino.
Use SSFC to separate touchscreen settings.

Bit 38-41 for TS_SOURCE:
(1) TS_UNPROVISIONED  -->  0
(2) TS_GTCH7503       -->  1

BUG=b:277979947
TEST=(1) emerge-nissa coreboot
     (2) Test on craaskino with G2 touchscreen
     (3) Test on craaskino with elan touchscreen

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I636f21be39f26a617653e134129a11479e801ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-17 00:33:39 +00:00
Simon Zhou 2cf25eb74b mb/google/rex: Create screebo variant
Create the screebo variant of the rex0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:276814951
BRANCH=None
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_SCREEBO

Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-16 14:07:52 +00:00
Matt DeVillier e30d204d38 soc/intel/jasperlake: Hook up GMA ACPI brightness controls
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.

Tested by adding gfx register on google/magpie. Backlight controls
work on Windows 10 and Linux 6.1.

Change-Id: Iaa9872cd590c3b1298667cc80354ed3efd91c6c8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-16 14:06:57 +00:00
Bill XIE cd3545556e util/cbfstool: Qualify struct e820entry as packed
In order to accord with grub (see include/grub/i386/linux.h) and
comments for offsets of members of struct linux_params,
struct e820entry should be defined as __packed, otherwise,
sizeof(struct linux_params) will become 4224 (0x1080).

Fortunately, the affected area is usually not occupied.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I09955c90e4eec337adca383e628a8821075381d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-04-16 14:04:32 +00:00
Subrata Banik 7f66adbc71 soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.c
The patch moves API that gets the CSE FW partition information into
CSE Lite specific file aka cse_lite.c because the consumer of this API
is the cse_lite specific ChromeOS devices hence, it's meaningful to
move the cse lite specific implementation inside cse_lite.c file.

BUG=b:273661726
TEST=Able to build and boot google/marasov with this code change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I49ffaec467f6fb24327de3b2882e37bf31eeb7cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74382
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15 15:54:17 +00:00
Michał Żygowski 8e6fec441d Update vboot submodule to upstream main
Updating from commit id 5b8596ce:
    2sha256_arm: Fix data abort issue

to commit id 35f50c31:
    Fix build error when compiling without -DNDEBUG

This brings in 41 new commits.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I58f6740c34670ea5a501ff2ee8cfcf9d2a1c25e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-15 15:15:55 +00:00
Lean Sheng Tan dc08548ea8 soc/intel/tigerlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by
selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.

Purpose of this feature is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73738
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15 14:36:46 +00:00
Lean Sheng Tan ce68d68e00 soc/intel/alderlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by
selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.

Purpose of this feature is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).

TEST=Able to build and boot Starlab ADL laptop to OS.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73736
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-15 14:36:29 +00:00
Musse Abdullahi ab496bf177 soc/intel/meteorlake: Add B0 stepping CPU ID
This patch adds CPU ID for B0 stepping (aka ES2).
DOC=#723567
TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log.

Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com>
Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184
Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15 12:10:08 +00:00
Kyösti Mälkki 71fd3becf0 soc/intel/baytrail: Make acpi_madt_irq_overrides() static
Change-Id: Id362e023358054df2c4511fd108c313da868306d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74325
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15 05:14:37 +00:00
Kyösti Mälkki 69a13964ea sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have
special handling for the time being.

Change of aopen/dxplplusu is coupled with sb/intel/i82801dx.
Change of emulation/qemu-i440fx is coupled with intel/i82371eb.

For asus/p2b, this adds MADT LAPIC entries, even though platform
has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates
the MADT, including an entry for LAPIC address.

Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-15 05:14:14 +00:00
Felix Held 0854f67cae ec/acpi/ec: replace misleading "recv_ec_data_timeout" console output
In the non-timeout case in recv_ec_data_timeout, a message like this one
will get printed at BIOS_SPEW log level: "recv_ec_data_timeout: 0x00".
The "timeout" part of the function name corresponds to what the function
does, but the message will only be printed when not running into the
timeout which is a bit misleading and might suggest a problem when there
is none. To avoid this possible confusion, don't use the function name
in the printk, but use "Data from EC:" instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I521f67517f64fc64e24853d96730c3f9459f1ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74381
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-14 23:47:29 +00:00
Kyösti Mälkki e39a3e3920 cpu,soc/intel: Sync ACPI CPU object implementations
Take variable names from soc/intel and adjust counter to
start from zero.

Change-Id: I14e1120e74e1bd92acd782a53104fabfb266c3b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14 17:35:56 +00:00
Elyes Haouas 9ac50e1575 cpu,soc/intel: Use acpigen_write_processor_device()
Use acpigen_write_processor_device() instead of deprecated
acpigen_write_processor().

Change-Id: I1448e0a8845b3a1beee0a3ed744358944faf66d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72488
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14 17:33:25 +00:00
Lean Sheng Tan d33cbf1803 soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB
that was caused by the API change in commit 36e6f9bc04. This patch removes the
broken API function and also adds package_id log print same as previous
commit mentioned above.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74436
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-14 15:23:47 +00:00
Felix Held 8f57fa5091 vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case
When a mainboard selects ACPI_SOC_NVS and CHROMEOS, CHROMEOS_NVS will be
selected. This causes vc/google/chromeec/acpi/chromeos.asl to be
included in the DSDT and chromeos_acpi_gpio_generate to be called when
generating the coreboot SSDT. When a mainboard also uses
DECLARE_NO_CROS_GPIOS(), this will cause variant_cros_gpio.count to be 0
and variant_cros_gpio.gpios to be NULL. chromeos_acpi_gpio_generate only
checked if the GPIO table was non-NULL, which caused the function to
exit early and not generate the OIPG package which causes the kernel to
complain about referencing the non-existing OIPG package. To avoid this,
only exit in the GPIO table pointer being NULL case if the number of
GPIOs is non-0.

TEST=Error about missing OIPG ACPI object in dmesg disappears on birman.

Before:

[    0.241339] chromeos_acpi: registering CHSW 0
[    0.241468] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.GPIO.OIPG], AE_NOT_FOUND (20220331/psargs-330)
[    0.241703] ACPI Error: Aborting method \CRHW.GPIO due to previous error (AE_NOT_FOUND) (20220331/psparse-531)
[    0.241933] chromeos_acpi: failed to retrieve GPIO (5)
[    0.242011] chromeos_acpi: registering VBNV 0
[    0.242113] chromeos_acpi: registering VBNV 1
[    0.242284] chromeos_acpi: truncating buffer from 3072 to 1336
[    0.242462] chromeos_acpi: installed

With the patch applied:

[    0.242580] chromeos_acpi: registering CHSW 0
[    0.242714] chromeos_acpi: registering VBNV 0
[    0.242817] chromeos_acpi: registering VBNV 1
[    0.242990] chromeos_acpi: truncating buffer from 3072 to 1336
[    0.243249] chromeos_acpi: installed

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74375
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14 14:48:36 +00:00
Subrata Banik ae0c84f987 soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
This patch avoids cannonlake base config to select eNEM for CAR by
default. Rather allow other SoC config to choose the applicable CAR
mode between eNEM and NEM.

CML and WHL select eNEM whereas CFL decided to use NEM for CAR setup.

Here is some background about why CFL SoC platform decided to choose
NEM over eNEM:

It was found that some coffeelake CPUs like Intel i3 9100E fail to enter
CAR mode because some MSR used by NEM enhanced are lacking. According to
the Intel SDM CPUID.EAX=07h.ECX=0 reg EBX[12 or 15] should indicate the
presence of IA32_PAR_ASSOC and CPUID.EAX=10h.ECX[1 or 2] reg ECX[2]
should indicate IA32_L3_QOS_CFG and IA32_L2_QOS_CFG respectively but
even on a Intel coffeelake CPU that works with the NEM_ENHANCED these
CPUID bits are all 0 so there is no way of knowing whether NEM_ENHANCED
will work at runtime. Instead just always use regular NEM.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14 14:45:12 +00:00
Ruihai Zhou 0db0d20c00 mb/google/corsola: Add detachable Starmie as variant
The 'Starmie' is a mt8186 detachable reference design that will share
most of Corsola design. For AP firmware, there will be a few changes,
mostly in display (MIPI interface and w/o bridge), so we create it
as a variant in Corsola.

BUG=b:275470328
BRANCH=corsola
TEST=./util/abuild/abuild -t google/corsola -b starmie -a

Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-14 12:09:56 +00:00
Cong Yang f9d72e3745 soc/mediatek: Add assert for regulator VRF12
Add assert for MT6366_VRF12, define a constant macro for 1200000.

BUG=none
TEST=build board starmie with mt8186.

Change-Id: I6d6a969ae993afcda0596a19928e8f98f343d589
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74394
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-14 12:09:24 +00:00
Cong Yang 4eba95d1b3 mb/google/corsola: Add support for VIO18 in regulator.c
Add regulator VIO18 support to supply power for STA_HIMAX83102_J02 panel.

BUG=b:272425116
TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie.

Change-Id: Ie1dd9226b0c4f05f9c9ce6633b7384aa5eb4c978
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74342
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14 12:08:41 +00:00
Cong Yang de7e014067 soc/mediatek: Add support for regulator VIO18
To provide power to MIPI panel STA_HIMAX83102_J02, add support for
regulator VIO18.

BUG=b:272425116
TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie.

Change-Id: I3c3aa105e648b87fc39f881d762002f67b4422b5
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74341
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
2023-04-14 12:08:14 +00:00
Arthur Heymans 36e6f9bc04 soc/intel/xeon_sp: Don't sort struct device cpus for numa
Currently the xeon_sp code reassigns struct devices apic_id so that srat
entries can be added in a certain order.

This is not a good idea as it breaks thread local storage which contains
a pointer to its struct device cpu.

This moves the sorting of the lapic_ids to the srat table generation
and adds the numa node id in each core init entry. Now it is done in
parallel too as a bonus.

Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68912
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14 10:50:44 +00:00
Kapil Porwal 4e498e169e soc/intel/meteorlake: Replace assert with error message
Avoid asserts related to CNVi UPDs which are not boot critical.
Instead, add error messages which are more helpful in identifying
the issue.

BUG=none
TEST=Boot to the OS on google/rex

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I49a988b7eda009456d438ba7be0d2918826e1c36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74370
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-14 09:46:16 +00:00
Benjamin Doron f43132e20c drivers/efi: Fix linker error when SMM phase uses option API
For security reasons, removing the efivars implementation of the option
API was considered. However, this use-case is not the "None"
option-backend (CONFIG_OPTION_BACKEND_NONE), so the SMM phase also does
not use the no-op in option.h. This causes linker errors when the
option API is called.

For example, src/soc/intel/common/block/pmc/pmclib.c and
src/console/init.c use `get_uint_option`.

Minimising code in SMM can be implemented as a follow-up.

Change-Id: Ief3b52965d8fde141c12266a716f254dd45559d5
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-14 09:41:53 +00:00
Kyösti Mälkki 199ccf81dd cpu/intel/speedstep: Refactor P-state coordination
Change-Id: I12462f271821d3d8fe3324d84a65c2341729591e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14 08:45:07 +00:00