Commit Graph

33160 Commits

Author SHA1 Message Date
Michał Żygowski 7c07110923 nb/amd/pi/00730F01/state_machine: Add lost options
Add back options that were lost on postcar migration. Some of them
seem to be required for IOMMU initialization.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie9cc772d7fcbefded8bab88f9960fef663dc7217
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09 15:42:08 +00:00
Michał Żygowski 506b9c102c amd/agesa/state_machine: Add BeforeInitLate hooks
Add missing BeforeInitLate hooks in order to bring back certain options
that were lost on postcar migration. This will also allow to disable
CDIT again that caused AmdInitLate error on 00730F01.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1226e9c0c8a92920f2569ec0f85d0be0adcc9e30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-09 15:40:15 +00:00
Kyösti Mälkki e1e3289052 AGESA,binaryPI boards: Declare some IRQ tables static
Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-01-09 15:35:54 +00:00
Kyösti Mälkki 034cf6390f drivers/pc80/rtc: Separate {get|set}_option() support
Move things depending on option_table.h to a separate file.

Change-Id: Ib23fcd89bf4efef9072fcaea1d8699145c1f2983
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09 14:38:47 +00:00
Kyösti Mälkki cbf9571588 drivers/pc80/rtc: Separate {get|set}_option() prototypes
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.

Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09 14:37:33 +00:00
Kyösti Mälkki 2a0e3b25ea drivers/pc80/rtc: Remove duplicate cmos_chksum_valid()
Change-Id: I5a4b86921876c24cd1d310b674119b960c3d2fd6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38194
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09 14:37:06 +00:00
Ravi Sarawadi 3838701c84 soc/intel/tigerlake: Update Kconfig
Update Kconfig:
  - use CAR NEM mode for tigerlake only as NEM Enhanced is under debug
  - update GSPI, RP max device #s according to
    PCH EDS#576591 vol1 rev1.2
  - update UART M/N setting according to new PCH baseclock

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-09 14:35:56 +00:00
Patrick Rudolph c83bab62b3 acpi: Be more ACPI compliant when generating _UID
* Add function to generate unique _UID using CRC32
* Add function to write the _UID based on a device's ACPI path

ACPI devices that have the same _HID must use different _UID.
Linux doesn't care about _UID if it's not used.
Windows 10 verifies the ACPI code on boot and BSODs if two devices
with the same _HID share the same _UID.

Fixes BSOD seen on Windows 10.

Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-09 14:22:51 +00:00
Patrick Rudolph 5c8ff794a8 superio/common/ssdt: Make disabled PNP devices ACPI compliant
Always write a _HID, even for disabled PNP devices.

Fixes a BSOD on Windows 10.

Change-Id: I419a08bd6a3570fb4e1ae31bef4f9ccd6836fe1b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-09 14:22:29 +00:00
Angel Pons 1aba2a32e8 nb/intel/sandybridge: Make MCHBAR arithmetics consistent
Ensure that the operation order is always the same. This results in
changes to the binary, but the effective result is the same.

Change-Id: I9772832c60089b35889df7298e20a2bd02b35b00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-09 14:17:50 +00:00
Subrata Banik d5be4e4046 soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi
This patch creates a common instance of northbridge.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to
refer northbridge.asl from common code block.

TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(MCHC) presence after booting to OS.

Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09 08:25:12 +00:00
Aaron Durbin a8280e4cc0 drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option
The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer
being used in the code. There's a runtime check for supporting
fast read dual output mode of the spi flash. Remove the references
to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B.

Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08 17:18:20 +00:00
Patrick Rudolph a48e8f52d8 Make: Add supermicro/smcbiosinfo to tools
Build the smcbiosinfo tool with other tools.

Fixes possible race condition on jenkins.

Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-08 16:24:04 +00:00
Angel Pons 6779d2352c util/autoport: correct build errors of produced files
Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-08 14:25:23 +00:00
Elyes HAOUAS 38a4f2a974 nb/amd/pi: Fix typos
Change-Id: I79ec3a346edde0a63cf344352e58dfb78556dfd8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38244
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08 12:58:31 +00:00
Elyes HAOUAS 0bc9f0b827 src/lib: Fix typos
Change-Id: Ia1da6637cfca5ddbd0879ea271bc68bb881b92e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37563
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08 12:57:53 +00:00
Elyes HAOUAS 8250e2e2d5 src/include: Fix typos
Change-Id: I52302e99708bca2f1e5e45f52cacd42e05a5fbd5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37567
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08 12:57:31 +00:00
Ravi Sarawadi 6e33797841 soc/intel/tigerlake: Fix PMC config
Fix PMC base address for tigerlake.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-08 06:32:17 +00:00
Jamie Chen 0c89c297e6 mb/google/hatch: Remove fixed IccMax values
Remove fixed IccMax values for all domains.
IccMax will be selected by CPU SKU in
fill_vr_domain_config function.

BUG=b:145094963
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to device and checked the log.

Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-08 05:46:37 +00:00
Jamie Chen 3ccae2b7cd soc/intel/cannonlake: Add VR config for CML
Add VR config IccMax, DC and AC loadline defaults for CML.
Add cpu_pl2_4_cfg to switch two kinds of VR design.

BUG🅱️145094963
BRANCH:none
TEST:build coreboot and fsp with enabled fw_debug.
     Flashed to device and checked the log.
     All VR configs were set correctly.

Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-08 05:46:16 +00:00
Jamie Chen 6bb9aaf93f soc/intel/cannonlake: Add Comet Lake H SA 4+2 Device ID
This patch adds CML-H 4+2 SA DID into systemagent.c and report
platform.
According to doc #605546:
    CML-H (4+2) R1: 9B64h

BUG:none
BRANCH:none
TEST:build no error

Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
2020-01-08 05:46:06 +00:00
Johanna Schander 1c9746ceaf drivers/spi/flashconsole: Fix shadowing local variable
Commit c9b13594eb removed the g_ prefix from
global variables, leaving the local "offset" variable shadowing the
global one. This commit partially reverts this by renaming one of the
occations and converting the flushing logic to work on the
global object.

Change-Id: I246ebdcfd3b973e6a4aa3c15fc5f32497dcf8398
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-07 20:50:03 +00:00
Kyösti Mälkki 23063305dc drivers/pc80/rtc: Refactor some USE_OPTION_TABLE
Change-Id: I3a5004db021af6127de2f058bec9d84a985bae67
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38183
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07 18:41:26 +00:00
Kyösti Mälkki fd15c0b8fa drivers/pc80/rtc: Refactor clear_cmos variable
After refactoring it is more a status variable rather than
a request.

Change-Id: I50b8099a08b556129416cea50f0ce6fafe6c14cc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07 18:41:12 +00:00
Kyösti Mälkki 731e58e319 drivers/pc80/rtc: Remove stub for sanitize_cmos()
We only have a single call-site for this.

Change-Id: I7ab19c6ea4ef01334f4d229c5636b64f99c86119
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38182
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07 18:40:37 +00:00
Kyösti Mälkki bb5b9fee8c drivers/pc80/rtc: Remove stub for cmos_post_init()
We only have a single call-site for this.

Change-Id: Ia05a762691351b37cc59b39222fec737b29e913c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-07 18:40:20 +00:00
Kyösti Mälkki a581166820 drivers/pc80/rtc: Clean up some headers
Change-Id: I5b3f1da6581dd80264aaa9618227ac64e1966e8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38180
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07 18:40:02 +00:00
Kyösti Mälkki 1a9b7b50c7 drivers/pc80/rtc: Clean up some inlined functions
Change-Id: Ie73797b4e9a09605a0685f0b03cb85e9a3be93ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-07 18:39:35 +00:00
Nico Huber a0259b4273 mb/google/{beltino,jecht}: Drop SIO configuration lines
These are meaningless for boards without SIO devices.

Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-07 18:25:04 +00:00
Elyes HAOUAS 73be5f7211 src/mainboard: Fix typo
Change-Id: I8a486ce12d6a5f6de31afd279612dc37d3fffd83
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-07 16:47:03 +00:00
Elyes HAOUAS 596cb6cde6 nb/agesa/family14: Don't use _HID and _ADR
A device object must contain either a _HID object or an _ADR object,
but should not contain both.

Change-Id: I727116cbc38fcd264c684da6ce766ea5e854f58c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-07 16:20:11 +00:00
Peichao Wang 3de43e9541 mb/google/kahlee/treeya: Tune VIH and meet spec
According to vendor Bayhub requirement need tune VIH
make it meets spec
    --0x304(6:4) CLK = 3
    --0x304(3:0) DAT = 5

BUG=None
TEST=build firmware and measure VIH whether meets spec

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I4de9e6cfb37e3b76f7afc206cbe3396b8da2d6dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37458
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07 15:45:20 +00:00
Peichao Wang 2f72a204a7 mb/google/kahlee/treeya: tune eDP delay time to 20 ms
tune eDP delay time to 20 ms ensure satisfy panel spec

BUG=b:147270512
TEST=verify panel sequences by ODM.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07 15:44:53 +00:00
Subrata Banik e938fb78f9 soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL code
List of changes in this patch

1. Remove unused variables
2. Make use of absolute path
3. Define macros and use inside SA ASL
4. Rearrange code in nothbridge.asl to move MCRS object under _CRS

Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2020-01-07 15:19:01 +00:00
Patrick Rudolph cc0b6f18cd lib/crc_byte: Add CRC32 implementation
* Add CRC32 using polynomial 0x04C11DB7
+ Add macro to caculate CRC of a buffer

Change-Id: If98e4e12bb53a6e5123e94e8cdffde1eb3bc4b4b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37753
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07 08:38:58 +00:00
Patrick Rudolph 389c827943 acpigen: Add function to generate unicode names
The ACPI spec 6.3 chapter 6.1.10 states that _STR has to return a buffer
containing UTF-16 characters.

Add function to generate Unicode names and use it for _STR. It will
replace non-ASCII characters with '?'.

Use the introduced function in IPMI driver.

Fixes ACPI warning shown in fwts.

Change-Id: I16992bd449e3a51f6a8875731cd45a9f43de5c8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07 08:16:20 +00:00
Marshall Dawson 2dd3b5c0f8 util/amdfwtool: Add instances for APCB backup
Match each of the possible APCB items with a corresponding backup APCB.
A missing backup copy can prevent the system from booting.

Change-Id: I400194b2763239896214ea42cfe6fbeb8ed261a8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-06 23:27:36 +00:00
Aaron Durbin d701ef7475 drives/spi_flash: add spi_flash_cmd_write_page_program()
The SPI flashes that support page programming mode had duplicated
the logic for writing in every driver. Add
spi_flash_cmd_write_page_program() and use the common implementation
to reduce code size that comes from duplication. The savings is
~2.5KiB per stage where the spi flash drivers are utilized.

Change-Id: Ie6db03fa8ad33789f1d07a718a769e4ca8bffe1d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-01-06 15:00:50 +00:00
Patrick Rudolph 9e877ec60d util/supermicro: Add and use new tool smcbiosinfo
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.

Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.

You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID

Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.

Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works

No further validation is done on the firmware.

Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06 10:56:09 +00:00
Patrick Rudolph 9b5447b781 soc/intel/cannonlake: Add VR config for CFL, CNL and WHL
Add VR config IccMax, DC and AC loadline defaults and voltage regulator
maximum for all CFL, CNL and WHL.
This supports mainboards with replaceable CPUs and provides sane defaults
for boards that are missing the devicetree overwrite.
Remove the default IccMax to make use of the introduced lookup-table.

Also change some hex values to decimal.

I couldn't find CML datasheet, so those are left out for now.

Used Doc #337344 and #338023 Section 7.

Change-Id: I1d2e174157d468830cc0baf2a2d8295ef61a1a63
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37466
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06 10:06:37 +00:00
Subrata Banik 26e2eeb276 soc/intel/dnv: Remove commented out Kconfig option
Change-Id: Ibe646bad09dcfe348dcbfec439129b2d22ec4744
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06 04:53:31 +00:00
Kyösti Mälkki 391bb132be mb/*/*: Remove unused option_table.h includes
These should have been removed together with read_option().

Change-Id: Ia6f268ac4551de14f9821c789844adfdf428b843
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38177
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06 04:30:59 +00:00
Kyösti Mälkki 287910765d drivers/pc80/rtc: Swap cmos_write32() parameter order
Make it consistent with the more used cmos_write().

Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38178
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06 04:30:40 +00:00
Marshall Dawson 19be7b569e vc/amd/pi/00670F00: Fix typo in phony target declaration
Correct a copy/paste error for warn_no_agesa.

Change-Id: Ife2cca47f1f816f99395b33976d08826c53e3c3e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05 23:54:58 +00:00
Nico Huber e67f539de4 abuild: Allow proper build tests with USE_AMD_BLOBS=y
Properly build test AMD ports that rely on blobs, too.

Change-Id: Ia82f38d0e57f463ee33844c7afebb9dd602cef05
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-05 23:54:48 +00:00
Nico Huber 933e6ff02d Populate 3rdparty/amd_blobs/
Kconfig default paths already point into `3rdparty/amd_blobs/`.

Change-Id: Ibb6f12183c48c7c07f76e794b4971c8b75116333
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-01-05 23:54:24 +00:00
Marshall Dawson bd74b602cc pci_ids: Correct whitespace for all AMD, ATI, National Semi
Convert spaces to tabs to match surrounding definitions and fix
alignment for AMD products and prior assets.

Change-Id: I37f1b7826afab8e224fb2d411247d77ea32664df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-05 17:09:11 +00:00
Michał Żygowski 287ce5f1ee sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-05 17:01:48 +00:00
Angel Pons d913036e18 mb/sapphire/pureplatinumh61: Make devicetree prettier
Align contents, and fix some redundant comments.

Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05 00:12:56 +00:00
Angel Pons d1b80f0fc2 mb/sapphire/pureplatinumh61/devicetree.cb: Drop zero values
They default to zero already.

Change-Id: Ib888377f06d6fcb79cff5e30155971c17aa2597c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05 00:12:35 +00:00