Commit Graph

45 Commits

Author SHA1 Message Date
Philipp Deppenwiese 438b463a8f Documentation: Update index.md and move files
* Add more subdirectories and index.mds.
* Move "getting started" and "lessons" into sub-directories.
* Move "NativeRaminit" into northbridge/intel/sandybridge folder.
* Move "MultiProcessorInit" into soc/intel/icelake folder.
* Reference new files

Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26262
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-30 09:14:48 +00:00
Patrick Rudolph 90f515a14b Documentation: More markdown fixes after switching to sphinx
Fix markdown code to work with sphinx.

Change-Id: I52014494dc2d09731fe14ab527073352ada860d1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26544
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28 13:46:37 +00:00
Patrick Rudolph ebdeb4d07d Documentation/Intel/NativeRaminit: Style fixes
Fix tables and minor markdown bugs.

Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-15 15:48:18 +00:00
Nico Huber 3de303179a {mb,nb,soc}: Remove references to pci_bus_default_ops()
pci_bus_default_ops() is the default anyway.

Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08 03:01:04 +00:00
Subrata Banik 55b183f112 Documentation/Intel: Add MultiProcessorInit documentation
Add documentation for MP service PPI using EFI interface
on Intel 9th Gen Platforms.

Documented so far:
* Problem Statement
* New Design Proposal
* API interface
* Code Flow changes
* Benefits

BRANCH=none
BUG=b:74436746
TEST=none

Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25921
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08 02:58:26 +00:00
Elyes HAOUAS 0c80d2f8e3 Documentation/Intel/NativeRaminit: Remove trailing whitespace
Change-Id: I1d38aea07e2d9ffb89115410603a5beac5e4d44d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27 09:09:27 +00:00
Jonathan Neuschäfer f895216c4f Documentation: SandyBridge_registers.md: Add a title
This fixes the following error when using "make -C Documentation sphinx":

/.../Documentation/Intel/NativeRaminit/Sandybridge.md:32: WARNING:
toctree contains reference to document
u'Intel/NativeRaminit/SandyBridge_registers' that doesn't have a title:
no link will be generated

Change-Id: Id273b8dbc96465833b8e2b2e78c3bac8cd217d4b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-26 11:58:12 +00:00
Jonathan Neuschäfer 3eee533d93 Documentation: Sandybridge RAM init: Fix links for Sphinx/recommonmark
Add a dash before the links to other files to mark those files as
subpages, and avoid the following error:

  reading sources... [ 33%] Intel/NativeRaminit/Sandybridge
  Exception occurred:
    File "/usr/lib/python2.7/dist-packages/recommonmark/states.py", line 134, in run_role
      content=content)
  TypeError: 'NoneType' object is not callable

While at it, also spell these filenames correctly: Only
SandyBridge_registers.md is spelled in camel-case.

Change-Id: If92be7d2b61229d0315e1cc5204e951171612fee
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-26 11:57:14 +00:00
Jonathan Neuschäfer 7719d50352 Documentation/Intel: Adjust heading levels
Adjust the headings so that there is only one h1 tag per file.

Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-17 17:18:07 +00:00
Jonathan Neuschäfer 8ee93ae267 Documentation: Fix a bunch of typos
Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10 10:50:06 +00:00
Patrick Rudolph bf8db8d45b Documentation/Intel: Add NativeRaminit documentation
Add documentation for Intel native raminit on Intel SandyBridge.
Documented so far:
* Register
* Read training
* Frequency selection
* SMBIOS type 17 memory reporting
* Various Kconfig options and features

Change-Id: I3b977460ecb29c9a54e3fab82349982fca9918e7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-09 16:59:16 +00:00
Werner Zeh cbdf9762d7 Documentation/Intel/vboot: Remove double word *after*
Change-Id: I5332c5760987d6ca6e92ac8aae7f3d43e09e8e4e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-14 15:27:46 +00:00
Paul Menzel 0cdb505d26 Documentation/Intel/vboot: Fix spelling of *following*
Change-Id: I26cf3cb049fb5520c59316ff7397b0bcfe6ee48d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-03 15:25:44 +00:00
Martin Roth 4b18a922f0 Documentation: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

Unfortunately, some external websites and projects are spelling coreboot
with an uppercase C, so references to those pages can't be changed
without breaking the link.

Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-12 04:06:40 +02:00
Nico Huber 2e7f6ccafc fsp/gop: Add running the GOP to the choice of gfx init
The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:

  * Drop confusing config GOP_SUPPORT,
  * Add HAVE_FSP_GOP to chipsets that support it,
  * Make running the GOP an option for FSP2.0 by returning 0
    in random VBT getters.

Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08 14:58:29 +02:00
Paul Menzel a8843dee58 Use more secure HTTPS URLs for coreboot sites
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.

Run the command below to replace all occurences.

```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```

Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07 12:04:50 +02:00
Lee Leahy dcc4d43151 Documentation/Intel: Add vboot documentation
Add documentation which describes how to build and sign a coreboot image
which enables vboot.

TEST=None

Change-Id: Ie17b8443772f596de0c9d8afe6f4ec3ac4d4fef8
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03 23:05:59 +02:00
Lee Leahy d677d9cedd Documentation/Intel/Soc: Update Quark FSP build instructions
Update the FSP build instructions for Quark:
* Discuss multiple types

BRANCH=none
BUG=None
TEST=Build Quark FSP using new instructions

Change-Id: Ibc4bfe32d0eb3877d3b988bc185c73be58d44878
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16826
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30 01:18:04 +02:00
Lee Leahy dc54270210 soc/intel/quark: Pass in the memory initialization parameters
Specify the memory initialization parameters in
mainboard/intel/galileo/devicetree.cb.  Pass these values into FSP to
initialize memory.

TEST=Build and run on Galileo Gen2

Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15260
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08 17:59:20 +02:00
Lee Leahy 24ba659d08 Documentation/Intel: Add feature documentation table
Add table containing feature documentation:
* Feature name with link to specification or documentation
* Linux utility name with link to utility documentation
* EDK-II utility name with link to utility documentation

Change-Id: Ie33d8563320697c12b34974286bffcadf92c016e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15256
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08 17:58:52 +02:00
Lee Leahy 061e0fb9ac Documentation/Intel/Board: Update the Galileo checklist
Update the Galileo board implementation checklist.

TEST=Build and run on Galileo Gen2

Change-Id: I1c88e9500d304273a3176d8b034a805920aab9bb
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15137
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12 12:28:57 +02:00
Lee Leahy 40b41bc799 Documentation/Intel/Board: Add Galileo checklist
Add the Galileo implementation checklist.

TEST=None

Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15012
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-02 02:47:29 +02:00
Lee Leahy 2a8cc3064e Documentation/Intel/Board: Add analog switch link
Add link for TI TS5A23159 specification.

TEST=None

Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15003
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 22:02:03 +02:00
Lee Leahy 2d96be6484 Documentation/Intel: Update the documentation
index.html:
* Separate the sections on the main page
* Move the documentation links to the main page
* Add links for FSP 1.0 and 2.0 specifications
* Add link for UEFI specifications
* Add link to MinnowBoard MAX coreboot

fsp1_1.html:
* Use Integration instead of Documentation

SoC/quark.html:
* Move documentation to main page
* Update build instructions for CorebootPayloadPkg
* Remove FatPkg since it is now part of edk2 tree
* Add source location for QuarkFspPkg
* Add build instructions for QuarkFspPkg

TEST=None

Change-Id: I48bd1bf98a6d8bc43bdd3b4c51dfd119a1e0f61b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14882
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18 19:47:16 +02:00
Aaron Durbin bf1e481944 lib: remove FLASHMAP_OFFSET config variable
The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however
the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define.
Those 2 values are not consistent. Therefore, remove the Kconfig
variable and defer to the #define generated by fmdtool.

Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14765
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-11 21:32:44 +02:00
Lee Leahy a4d8180913 Documentation: x86 MTRR setup, TempRamExit and MTRR loading
Document how to test TempRamExit and verify the MTRR setup and loading.

TEST=None

Change-Id: I57a604fa139edac4b05453547d3caf185db491e0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 20:12:35 +01:00
Lee Leahy b953d05e60 Documentation/Intel: Add more Galileo Gen2 links
Add datasheet links for the components supporting GPIO.  This includes
I2C I/O ports, I2C PWMs, bus buffers and multiplexers.

TEST=None

Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14114
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:35 +01:00
Lee Leahy e9a6d1a813 Documentation: x86 shadow ROM disable
Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.

TEST=None

Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:06 +01:00
Lee Leahy fcfa94d6e8 Documentation/Intel: Add EDK-II links
Add a link to the "Driver Writer's Guide" and a link to the "EDK II
firmware for Intel Quark SoC X1000" document.

TEST=None

Change-Id: I8d629d06accfe24a0b8971b5b5868849587c3db7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13893
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-03-07 04:17:34 +01:00
Lee Leahy 7b209ddea7 Documentation/Intel: Making a bootable SD card
Add a link to "Making a bootable SD card"

TEST=None

Change-Id: I5682fdd51a4ba37f97ad35475e11d9843f1498fb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13892
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07 04:16:55 +01:00
Lee Leahy 4ee073d476 Documentation/Intel: More CorebootPayloadPkg documentation
Add more documentation on the features that the EDK-II
CorebootPayloadPkg is using.  Add 8254 and 8259 documentation
links.  Add EDK-II documentation links.

TEST=Boot CorebootPayloadPkg to shell prompt

Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29 04:59:26 +01:00
Lee Leahy ca20b5fa6f Documentation/Intel: Add ACPI link and more FADT documentation
Add a link to the ACPI specification.
Update the FADT table to better describe the use and ACPI specification
reference for the various fields.

TEST=None

Change-Id: I77cd925800d71398be6d677de48874099ea26479
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29 04:56:23 +01:00
Lee Leahy bf08da27d5 Documentation/Intel: Add minimal APCI and TempRamExit documentation
Update the documentation to add the minimal ACPI support.  Also add
TempRamExit entry to the FSP features table.

TEST=None

Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13757
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-24 15:55:42 +01:00
Lee Leahy c7a943397d Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructions
Update the build instructions for CorebootPayloadPkg to target the
Galileo Gen2 platform.

TEST=Build and run on the Galileo Gen2 platform.

Change-Id: I9ca8a67811eff988f81f04d4c01c77115356c050
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13756
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-22 07:06:54 +01:00
Lee Leahy de8c7e39bc Documentation: x86 device tree processing and memory map
Add documentation on:
*  FSP Silicon Init
*  How to start the x86 device tree processing for ramstage
*  Disabling the PCI devices
*  Generic PCI device drivers
*  Memory map support

TEST=None

Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13718
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:24:02 +01:00
Lee Leahy db7410e0a4 Documentation: x86 add EDK2 CorebootPayloadPkg and documentation links
Add EDK2 CorebootPayloadPkg build instructions, EDK2 documentation links
and EDK2 BIOS build instructions.

TEST=None

Change-Id: I236405914c5fa8e33a7826cc4fa60f6dbf0e7724
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13717
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:23:41 +01:00
Lee Leahy 1c85fea945 Documentation: Add Quark EDK2 build instructions for Linux
Document the Linux build instructions for EDK2.

TEST=Build EDK2 for Quark on Ubuntu 14.04

Change-Id: I5f87eb2c5879f2fd4dd18880908756089a0c7a51
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13644
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09 19:22:06 +01:00
Lee Leahy fcf776fd02 Documentation: x86 add sleep state and minimal memory setup
Document how to add the sleep state and minimal memory setup.

TEST=None

Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:57:25 +01:00
Lee Leahy 66decf1644 Documentation: x86 Enable Serial Output
Document the steps necessary to enable serial output

TEST=None

Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13444
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:57:03 +01:00
Lee Leahy 7e0078b990 Documentation: Add the x86 FSP Binary
Document how to add the FSP binary to the SPI flash image.

TEST=None

Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13442
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:53:11 +01:00
Lee Leahy a1e4de47c6 Documentation: Add Galileo Gen 1 Documentation
TEST=None

Change-Id: Ic5a732dc27e772c4708a090ecd0c0af17dc5b056
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13606
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:52:54 +01:00
Lee Leahy e8424cf10f Documentation: Fix links to Intel/documentation.html
Fix links to the documenation.html page which was renamed from
x86Documenation.html.

TEST=Verified documentation links and searched for x86Documenation.html

Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13592
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:52:46 +01:00
Lee Leahy 380e167680 Documentation: Add x86 bootblock support
Document what is involved with adding the bootblock support.

TEST=None

Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13441
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 19:30:40 +01:00
Lee Leahy 05c0215ff3 Documenation: x86 Quark/Galileo remove i586 warning
Leverage patch 13552 by adding USE_MARCH_586 to soc/intel/quark/Kconfig.

TEST=None

Change-Id: Ifac947db53e967b98b9494db3f6c3f8ee039ac73
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13561
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-02-02 19:00:13 +01:00
Lee Leahy c1e4f89953 Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for
x86.

TEST=None

Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02 15:54:43 +01:00