No longer fallback to UDELAY_IO as default.
Since these are not cpu properties or features,
move the Kconfig location.
Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
To clear all DRAM on x86_32, add a new method that uses PAE to access
more than 32bit of address space.
Add Documentation as well.
Required for clearing all system memory as part of security API.
Tested on wedge100s:
Takes less than 2 seconds to clear 8GiB of DRAM.
Tested on P8H61M-Pro:
Takes less than 1 second to clear 4GiB of DRAM.
Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This copies the makefile code from the smm/smm.o.
Now works with clang version 7.0.1 from my OS using
CONFIG_ANY_TOOLCHAIN.
Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30504
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes all possible dependencies in order to build platform
with CONFIG_RAMPAYLOAD enable(without ramstage).
A. Create coreboot separate stage kconfigs
This patch creates seperate stage configs as below
1. HAVE_BOOTBLOCK
2. HAVE_VERSTAGE
3. HAVE_ROMSTAGE
4. HAVE_POSTCAR
5. HAVE_RAMSTAGE
B. Also ensures below kconfigs are aligned with correct stage configs
1. COMPRESS_RAMSTAGE and RELOCATABLE_RAMSTAGE are now enable if
CONFIG_HAVE_RAMSTAGE is selected.
2. COMPRESS_BOOTBLOCK will enable if CONFIG_HAVE_BOOTBLOCK is set
3. COMPRESS_PRERAM_STAGES will enable if CONFIG_HAVE_VERSTAGE
|| CONFIG_HAVE_ROMSTAGE is selected.
C. Also fix compilation issue with !CONFIG_HAVE_RAMSTAGE
On x86 platform:
Case 1: ramstage do exist: CONFIG_HAVE_RAMSTAGE=1
>> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_x86_32
Case 2: ramstage doesn't exist: CONFIG_HAVE_RAMSTAGE=0
>> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_
This patch fixes Case 2 usecase where platform doesn't select
CONFIG_HAVE_RAMSTAGE.
Also add option to create sipi_vector.manual based on $(TARGET_STAGE)
variable.
$(TARGET_STAGE)=ramstage if user selects CONFIG_HAVE_RAMSTAGE
$(TARGET_STAGE)=postcar if user selects CONFIG_RAMPAYLOAD
Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The initialization logic for the fixed_msrs and msr_index arrays depends
on the contents of the fixed MTRR descriptor. However, Coverity is unable
to check these values and believes (incorrectly) that the arrays may not
be entirely initialized. An assert was added in commit b28025a434 to
ensure that one of the loops is entered, but it is simplest to just
check that msr_num has iterated over the entire array after the loops
are over. This also acts as a sanity check that the values in the MTRR
descriptor were hardcoded correctly.
Change-Id: Ia573792f74aa6ea5e659c1e2253f112184fbb0a5
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1370582
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Added missing new line to Info Output.
Change-Id: Ic4cd63f231de918fad7cd34724651bf8eb1c8e62
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Previously cpu_index() always succeeded, but since commit 095c931
(src/arch/x86: Use core apic id to get cpu_index()) it is now possible
for it to indicate an error by returning -1. This commit adds error
handling for all calls to cpu_index(), and restores several checks that
were removed in commit 7c712bb (Fix code that would trip -Wtype-limits)
but are now needed.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5436eed4cb5675f916924eb9670db04592a8b927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch ensures start_cpu() function to store default_apic_id using
common cpu_add_map_entry() function to make cpu_index() implementation
generic.
BRANCH=none
BUG=b:79562868
Change-Id: Iac4d6e9e6e6f9ba644335b4b70da8689c405f638
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch renames mp_get_apic_id() to cpu_get_apic_id() and
add_cpu_map_entry() to cpu_add_map_entry() in order access it
outside CONFIG_PARALLEL_MP kconfig scope.
Also make below changes
- Make cpu_add_map_entry() function available externally to call
it from mp_init.c and lapic_cpu_init.c.
BRANCH=none
BUG=b:79562868
Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Checking for empty MTRR_DEF_TYPE_MSR as a proxy for proper CPU reset
is common across multiple platforms. Therefore place it in a common
location.
Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This IS_ENABLED(XXX) line should've clearly been IS_ENABLED(CONFIG_XXX).
This patch fixes the issue. Not tested on a real board, but looking at
the affected code paths suggests that this will result in no effective
change anywhere (since CAR should already be torn down by the time this
is called on FSP1.0 boards, so do_car_migrate_variables() would have
immediately exited anyway).
Change-Id: I74e0ed4d04471ee521ff5c69a74a6f4c949e5847
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Static scan does not know the contents of the fixed MTRR descriptor, so
it has no way to eval the result for variable num_ranges. If num_ranges
is less or equal to 0, the for loop will not be entered, and the values
of fixed_msrs will not be set. Asserting that num_ranges is greater than
0 ensures the loop enters at least once.
BUG=b:112253891
TEST=build grunt
Change-Id: Ieec0ac432c745bde4b1700539c266625da6cfd77
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The SMI handler on qemu returned early, due to missing SMM-Revision
Level support.
Add the ID qemu uses, which is AMD64 compatible for qemu-system-x86_64.
Fixes booting tianocore payload with SMM variable store on qemu.
Change-Id: I978b94150cfc49a39c2a0818eb14a649850e451d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Followup removes SIPI_VECTOR_IN_ROM and it seems reasonable
enough to force the alignment unconditionally to page size.
Reason for the conditionals is the alignment is not possible
with romcc bootblocks having total size less than 4 kiB.
Change-Id: I0ff2786f80a319ebb3215d4fd696cda3e15c3012
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When rmodule is loaded CPU stack alignment is only guaranteed
to 4kiB. Implementation of cpu_info() requires that each
CPU sees its stack aligned to CONFIG_STACK_SIZE.
Add one spare CPU for the stack reserve, such that alignment can
be enforced runtime.
Change-Id: Ie04956c64df0dc7bb156002d3d4f2629f92b340e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26302
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was used to check romcc-built bootblock and romstage
agree about the location of 16-bit entrypoint. There was
no need to customize it as bootblock size requirement did
not grow. Just check for a fixed location at 4 GiB - 4 KiB.
With C_ENVIRONMENT_BOOTBLOCK we can have a proper symbol
for the purpose, since it appears in the same compilation
unit. It will adjust if C_ENV_BOOTBLOCK_SIZE changes.
Change-Id: I93f3c37e78ba587455c804de8c57e7e06832a81f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This function returns APIC id for respective cpu core.
BUG=b:74436746
BRANCH=none
TEST=mp_get_apic_id() can be accessed in other files now.
Change-Id: I5c5eda8325f941ab84d8a3fe0dae64be71c44855
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/25620
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All i82801gx targets now use SMM_TSEG.
Change-Id: Ib4e6974088a685290ed1dddf5228a99918744124
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel DG41WV, resume from S3 still works fine.
Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
No need to hide prompts, it's a user choice anyway, they should know.
The help texts were just rephrasing the prompts or stating the obvious.
Change-Id: I5694a88f2da57af2a20357c4e22c7c648053cc26
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29802
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Gather x86 specific debug options and deflate their code a little. We
keep their hiding rules and help texts, although they don't seem much
useful.
Change-Id: I3bb8e759fc6a4871d30fccff47babfb7a291b45c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29751
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A stack overrun has been observed on AMD64 CPUs during the SMM module
relocation process. Change the assumed required size from equaling the
save structure's size to a Kconfig symbol.
A value of 0x400 doubles the size used by AMD64 systems and maintains
the size used by EM64T.
BUG=b:118420852
TEST=S3 on Grunt and verify 0x2f000-0x30000 uncorrupted
Change-Id: Ib1d590ee4afb06ca649afd6ad253cdfd969ae777
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Add a __always_inline macro that wraps __attribute__((always_inline))
and replace current users with the macro, excluding files under
src/vendorcode.
Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
Kyösti Mälkki