Commit Graph

18239 Commits

Author SHA1 Message Date
Patrick Georgi 33ab4fea23 libpayload: fix leak in libcbfs
stage wasn't freed on errors.

Change-Id: I10d2f42f3e484955619addbef2898981f6f90a35
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347345
Reviewed-on: https://review.coreboot.org/15958
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 20:01:10 +02:00
Fabian Kunkel 41b3196bc8 mainboard/bap/ode_e20XX: Enable UART 3/4 in devicetree
This patch adds IO and IRQ information for UART 3/4 to the devicetree.
Patch with Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e is needed.
Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0

Change-Id: I1d8fa16950079a47775f48166486415bd5d24f42
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15621
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31 20:00:47 +02:00
Fabian Kunkel 8cab72e1d8 mainboard/bap/ode_e20XX: Add different DDR3 clk settings
This patch adds two SPD files with different DDR3 clk settings.
The user can choose which setting to use.
Lower clk settings saves power under load.
SoC Model GX-411GA supports only up to DDR3-1066 clk mode.
Both SPD settings were tested with memtest for several hours.
Power saving is around half a watt under heavy memory load.
Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0

Change-Id: Ibb81e22e19297fdf64360bc3e213529e9d183586
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15907
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31 20:00:14 +02:00
Fabian Kunkel 1f9c07fcd7 mainboard/bap/ode_e20XX: Change PCIe lines
This patch binds PCIe lanes 2 and 3 to one PCIe device.
PCIe device 2.4 becomes x2.
Tested with the connected FPGA on PCIe 2.4.
FPGA doubles transfer rate from/to the AMD.
Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0

Change-Id: Icee567272312a7df4c3b5a6db5b420a054ec3230
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15905
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31 19:58:12 +02:00
Omar Pakker 449fb9b6eb superio/nuvoton: Add Nuvoton NCT6791D
This adds support for Nuvoton NCT6791D Super I/O chips.
Makes use of the common Nuvoton early_serial.c.

Based on the Datasheet supplied by Nuvoton.
Datasheet Version: January 8th, 2016 Revision 1.11

Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15967
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-07-31 19:42:49 +02:00
Elyes HAOUAS 2a600263dc src/vboot: Capitalize RAM and CPU
Change-Id: Iff6b1b08b8159588b964d9637b16e1e0bfcca940
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 19:31:41 +02:00
Elyes HAOUAS 91e0e3ccbe src/lib: Capitalize ROM, RAM, NVRAM and CPU
Change-Id: Id0871b0c2eb31e2d728180b44cc5b518b751add4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15985
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 19:30:54 +02:00
Elyes HAOUAS 7753731f0c src/drivers: Capitalize CPU, RAM and ACPI
Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15983
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 19:29:22 +02:00
Elyes HAOUAS 038e7247dc src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 19:27:53 +02:00
Elyes HAOUAS f9e7d1b0ca src/acpi: Capitalize ACPI and SATA
Change-Id: I7a4f1bd5c9e3c8152ebdd9118adddbc526d03a53
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15959
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 19:25:40 +02:00
Patrick Georgi 2660a1321a sunw/ultra40m2: Fix handling non-existence of a device
This probably never happens, but since we already test for the presence
of the device, it makes no sense to try to configure it after its
absense was determined.

Change-Id: I9877dcd15819fb7949fa08a0954b05780df66316
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347362
Reviewed-on: https://review.coreboot.org/15982
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31 19:25:04 +02:00
Patrick Georgi 1fcebe7fd9 intelvbttool: cope with errors in open()
Change-Id: I9fee87b7331ee05d4e984cb024f124abb2c97a69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347357
Reviewed-on: https://review.coreboot.org/15962
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 19:23:29 +02:00
Patrick Georgi c091604363 sis/sis966: fix typo
temp8 & (!0x10) == temp8 & 0 == 0, which is certainly not intended.

Change-Id: Ie9f735d31eedbec171f82929a147fc1b2e30b45a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1229587
Reviewed-on: https://review.coreboot.org/15961
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 19:20:27 +02:00
Patrick Georgi 21ce6efe28 sis/sis966: don't store a 32bit value in a 16bit variable
That only makes deviceid == 0 (because shifting a 16bit value by 16
bits, well...)

Change-Id: Iddca1de20760f92f70fe2d05886b488e5b48313d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1229558
Reviewed-on: https://review.coreboot.org/15960
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 19:19:33 +02:00
Patrick Georgi e8c413318f libpayload: Drop superfluous "continue"
Change-Id: I5a1d1ce8ba268b08d1275f392f0b9e602860c6ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260729
Reviewed-on: https://review.coreboot.org/15957
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
2016-07-31 19:17:27 +02:00
Patrick Georgi 030c73031d util/inteltool: fix memory leak
A struct pci_dev was allocated but not freed.

Change-Id: I6a8bbef6a118fc1f0aa7037e72c4d0dda9208f4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1353037
Reviewed-on: https://review.coreboot.org/15971
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 19:16:45 +02:00
Patrick Georgi be8f0fa2bb util/cbmem: Initialize variable
There can be cases where "found" wasn't initialized, do so.

Change-Id: Ifef8d61daa70e27ec39b7a8f3481d2316dfaa36e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347334
Reviewed-on: https://review.coreboot.org/15969
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 19:15:34 +02:00
Patrick Georgi 8260650cde nvramtool: Don't consider reserved regions to be "out of range"
Reserved regions showed different behavior for debug and regular builds.
Debug output was unfriendly, regular was wrong.
Print a proper error message and exit instead.

Change-Id: I9842ff61f7d554800e2041e8c4c607f22b2df79f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1287076
Reviewed-on: https://review.coreboot.org/15968
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 19:07:43 +02:00
Patrick Georgi e8f2ef51e1 intel/broadwell: fix typo
(pci_read_config32(...) > 14) & 0x3 looks rather unusual (and prevents
"case 3" below from ever happening)

Change-Id: Id90655c39ff53da9569441278bbf73497d643480
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1293139
Reviewed-on: https://review.coreboot.org/15965
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 19:01:56 +02:00
Patrick Georgi 90ed31beac intel/skylake: Enable signalling of error condition
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn
returns an int (with -1 for "error"), so use int for devfn.

Change-Id: I7d1cdb6af4140f7dc322141c0c018d8418627434
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1357450, #1357449
Reviewed-on: https://review.coreboot.org/15964
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 19:00:00 +02:00
Furquan Shaikh bce1807d9c google/reef: Update chromeos.fmd RO_SECTION
Update RO_SECTION to match the changes in depthcharge:
https://chromium-review.googlesource.com/#/c/364261

BUG=chrome-os-partner:55713

Change-Id: I7238856cf73a62345778ea87e191a11190b7fb38
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15966
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:59:10 +02:00
Shaunak Saha b97cf79e2e intel/amenia: Enable DPTF in mainboard
This patch enables DPTF support for Intel Amenia
platform, adds the ASL settings specific to Amenia
boards.

BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
       under /sys/class/thermal in Amenia board. Navigate to
       /sys/class/thermal, and verify that a thermal
       zone of type TCPU exists there.

Change-Id: I400e2312a20870058f3a386004fad748d3ee4460
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15094
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 18:57:59 +02:00
Shaunak Saha 57f221e6c4 google/reef: Enable DPTF in mainboard
This patch enables DPTF support for Google Reef
platform, adds the ASL settings specific to Reef
boards.

BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
       under /sys/class/thermal in Reef boards. Navigate to
       /sys/class/thermal, and verify that a thermal
       zone of type TCPU exists there.

Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15640
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 18:57:23 +02:00
Paul Menzel c663a1f033 gigabyte/ga_2761gxdk: Remove comment *endif*
After the indentation is fixed in commit *mainboard: Format
irq_tables.c* [1], the comment is redundant. So remove it.

[1] Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a

Change-Id: Iebbcf10ee3cef1b4cf60ea34a6b3ad51e2208671
Reviewed-on: https://review.coreboot.org/15933
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 18:44:47 +02:00
Paul Menzel 95fe8fb1e0 mainboard: Format irq_tables.c
Run the command below to format the files `irq_tables.c` of (mostly AMD)
mainboards correctly with GNU indent 2.2.10.

```
$ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l
```

Fix up the following two checkpatch.pl errors manually.

```
ERROR: that open brace { should be on the previous line
#1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129:
+			uint8_t reg[8] =
+			    { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 };

ERROR: that open brace { should be on the previous line
#1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131:
+			uint8_t irq[8] =
+			    { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 };

```

This is needed, so that follow-up commits, fixing checkpatch.pl errors
and warnings, won’t run into conflicts with the git commit hooks, when
for example, spaces instead of tabs are used for indentation.

Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/15932
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31 18:44:00 +02:00
Patrick Georgi 14caed85e1 build system: really disable building CrEC when not needed
Enable users to set the EC_EXTERNAL_FIRMWARE config flag, and actively
ignore anything related to EC firmware board names if enabled.

BUG=none
BRANCH=none
CQ-DEPEND=CL:344540
TEST=emerge-samus coreboot works

Change-Id: I02aa1e4bc0c98300105b83a12979e9368a40cbcf
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4f0b6fd10aa89fbb38bdebf14b8a82d52e9ee233
Original-Change-Id: I39c3038d059ec3d7710b864061fcf83b8d6d4d13
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/345584
Original-Reviewed-by: Aaron Durbin <adurbin@google.com>
Original-Commit-Queue: Martin Roth <martinroth@chromium.org>
Original-Trybot-Ready: Martin Roth <martinroth@chromium.org>
Original-Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15938
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-31 18:39:20 +02:00
Omar Pakker 312e9f586a superiotool: Add Nuvoton NCT6791D
This adds support for the Nuvoton NCT6791D Super I/O chip to the
superiotool.
The implementation is based on the Datasheet supplied by Nuvoton:
Datasheet Version: January 8th, 2016 Revision 1.11

Datasheet deviation:
- Defaults for control registers 0x20 and 0x21 are invalid.
  Datasheet: 0xc562. Actual: 0xc803.

Change-Id: I8ced9738cd41960cbab7b5ea38ff19192d210672
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15252
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31 18:35:59 +02:00
Elyes HAOUAS 777ea897e8 src/arch: Capitalize CPU, RAM and ROM
Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15953
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 18:35:09 +02:00
Elyes HAOUAS 45de1fe4fb src/Kconfig: Capitalize ROM
Change-Id: I6c090f5adcc46b4e069a156c6b506a76c0aa7cb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 18:34:16 +02:00
Elyes HAOUAS fa640a2f56 src/device: Capitalize CPU, RAM and ROM
Change-Id: I133531391a20261e0926524d70c0901079076af9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:33:30 +02:00
Elyes HAOUAS d82be923b1 src/cpu: Capitalize CPU
Change-Id: I58d5c16de796a91fa14d8db78722024266c09a94
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15934
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 18:33:06 +02:00
Elyes HAOUAS 918535a657 src/include: Capitalize CPU, RAM and ROM
Change-Id: Id40c1bf868820c77ea20146d19c6d552c2f970c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15942
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 18:30:16 +02:00
Elyes HAOUAS 1bcd7fcb61 src/southbridge: Capitalize CPU, RAM and ROM
Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15941
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
2016-07-31 18:29:13 +02:00
Elyes HAOUAS 15279a9696 src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 18:28:48 +02:00
Elyes HAOUAS 585d1a0e7d src/cpu: Capitalize ROM and RAM
Change-Id: I103167a0c39627bcd2ca1d0d4288eb5df02a6cd2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:28:27 +02:00
Stefan Reinauer 9071670a84 nvidia/tegra124: Adjust memlayout to Chrome OS toolchain
The bootblock gets slightly too big, so adjust the space assigned to
it.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=emerge-nyan coreboot works again.

Change-Id: Ib44d98692ae88c7cd3610c8e643d7d48ac858161
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4b9038b018ed7a26fbce01d982b22166b328de37
Original-Change-Id: If494e49fb60c11e01ca780c84036ebf24459628c
Original-Reviewed-on: https://chromium-review.googlesource.com/346492
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Queue: Stefan Reinauer <reinauer@google.com>
Original-Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/15950
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:27:39 +02:00
Kan Yan 08492f70b7 google/gale: Change board ID definition.
Change EVT3 board id to 5.

BUG=chrome-os-partner:55320
TEST=None.
BRANCH=None

Change-Id: I020be47e1fdbf886c7c471d7fdcace1537875b6d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 63bd6541055172765c31a9b1220a24d4e3604cdc
Original-Change-Id: I21a8764ff95892430944778f4898d2f1d4c97fd7
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/362391
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/15949
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:26:53 +02:00
Martin Roth 5ae61d94e7 Update degree symbol to utf-8 encoding in comments
Almost all of the places where we have the degree symbol '°', it's
encoded as 0xc2 0xb0 (utf-8 encoding).  There are a few places where it
is encoded as just a high ascii byte: 0xb0.  Editors that support the
high ascii 0xb0 seem to support the utf-8 0xc2 0xb0 encoding as well,
but the opposite does not seem to be true.

Change the high-ascii degree symbols to utf-8 encoding.

Change-Id: I3d06289b802f45e938dc72b4c437fca56235b62b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15978
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:24:54 +02:00
Martin Roth 4c72d3612b Remove extra newlines from the end of all coreboot files.
This removes the newlines from all files found by the new
int-015-final-newlines script.

Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:19:33 +02:00
Nico Huber 4b48ed8f38 buildgcc: Apply patches with -p1
Turned out that there are versions of the patch command that use the
left hand side path for new files created by a patch. This behavior is
incompatible with some of our patches. Stripping the topmost dir from
the path with -p1 helps.

While touching that line, I couldn't resist to drop a command
substituion (the `echo $patch`). It really shouldn't be necessary as the
path to the patch file is already expanded in the head of the for loop.

Change-Id: I95398605db6dd54a8b08d8bc84c6602edbea6e10
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/15908
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
2016-07-31 17:37:41 +02:00
Kyösti Mälkki 828e73e0b6 intel/wifi: Include conditionally in the build
Keep this enabled by default as most x86 platforms could have PCI-e
slots equipped with one of these Intel WiFi adapters.

The Kconfig entries under google boards had no function previously,
the variable was never referenced.

Change-Id: I728ce3fd83d51d4e5e32b848a2079c5fcee29349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15931
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 00:07:47 +02:00
Antonello Dettori 783d0c146f bayou: delete pbuilder utility
Delete pbuilder since it is not needed anymore.

Change-Id: I685547e9692944b89521864fc3bee4e9a2f1139f
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15955
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-30 19:34:36 +02:00
Stefan Reinauer 28434a9ca7 util/chromeos: Make scripts executable
crosfirmware.sh and extract_blobs.sh are not executable, change that.

Change-Id: Ib04df580a9acd4a422aedbdc15013b2ef505459a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15922
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-30 19:34:20 +02:00
Fabian Kunkel cf05183d1f mainboard/bap/ode_e21XX: Add board support
Add next generation of BAPs (https://www.unibap.com/) SOC module,
called ode_e21XX.
Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini),
but it includes a new AMD G-Series GX-412HC (Steppe Eagle)
and an updated Microsemi FPGA.
Changes to Olivehillplus:
- Add SuperIO Fintek F81866D
- Soldered down DDR3 with ECC
- User can choose between different DDR3 clk settings
(lowest setting can save up to 1.2W)
- Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3

Tested with:
- Payload SeaBIOS 1.9.1
- Lubuntu 16.04, Kernel 4.4.0
- Windows 10 (UART functionality)
Known problems:
- S3 not working
- IOMMU not working

Change-Id: I41f6a3334ad2128695a3f7c0a6444f1678d2626e
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15918
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30 06:51:13 +02:00
Fabian Kunkel 171e2c965a mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus
Initial copy of olivehillplus.

Change-Id: Ibe9b450c05bfad15a95852addb1465ac2d3cef61
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15917
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-30 06:49:55 +02:00
Aaron Durbin b0f81518b5 chromeos mainboards: remove chromeos.asl
Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30 01:36:32 +02:00
Furquan Shaikh 212820c8d7 google/reef: Use GPE0_DW1_15 as wake signal for touchpad
Due to GPE routing, raw GPIO cannot be used for indicating the wake
signal for touchpad. Instead we need to reference GPE pins.

BUG=chrome-os-partner:55670

Change-Id: Ie5d8473df4301c7beef0cae8fe84e71b2838261b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15947
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30 00:53:38 +02:00
Furquan Shaikh 6e37e90193 soc/intel/apollolake: Include gpe.h in chip.h
This is required for using GPE_* macros in devicetree.cb.

BUG=chrome-os-partner:55670

Change-Id: I8f6f536df96cf8145bb0c03ec413fb2f374301b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15946
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30 00:53:27 +02:00
Zhuo-hao.Lee ce37e47f46 skylake: fix VSDIO is at 0.8V when SDCard is not inserted
1. Enable SoC SD_CMD/D* signals pull-down of 20k when SD-card
   is removed. When SD-card is disconnected, the pull-down is
   disabled.
2. Provide path for weak leakage from buffers of SD_CMD/D* signal
   to be grounded. Thus dropping voltage on the SD_CMD/D* signals to ~0V.

BUG=chrome-os-partner:54421
TEST=no power leakage when SDCard isn't inserted on skylake platform

Change-Id: I567199b172841125f8916a61a76005cfdaa62eb8
Signed-off-by: Zhuo-hao.Lee <zhuo-hao.lee@intel.com>
Reviewed-on: https://review.coreboot.org/15910
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-29 00:12:53 +02:00
Abhay Kumar ec2947fb07 soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume
Do not pass VBT table to fsp in normal mode and S3 resume so that
PEIM GFX will not get initialized.

Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-29 00:09:05 +02:00