Commit Graph

37223 Commits

Author SHA1 Message Date
Maxim Polyakov 922c67bd35 mb/up/squared/gpio: 1/3 Decode raw register values
Use the intelp2m utility [1] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fiends macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:

./intelp2m -ii -fld cb -t 1 -p apl -file ./up-gpio.h

This is part of the patch set
"mb/up/squared: Rewrite pad config using intelp2m":

CB:42608 - 1/3 Decode raw register values
CB:42915 - 2/3 Exclude fields that are not in PAD_CFG*
CB:39765 - 3/3 Converts bit field macros to PAD_CFG

[1] https://review.coreboot.org/c/coreboot/+/35643

Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: I2523439af8842365c7de901bdfad85ad16d25dcf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:19:51 +00:00
Iru Cai 12a13e1f30 nb/intel/haswell: Add Crystal Well PCI IDs
From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs
use some new PCI IDs. Without this patch, the Crystal Well northbridge
cannot be initialized in ramstage, thus the machine cannot boot. Some
PCI IDs of Crystal Well related devices can be found in the PCI ID
database [2].

Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. The board
boots to SeaBIOS with boot screen displayed on HDMI output, and then
boots Arch Linux on a USB disk.

[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/DNHLQTNTRQT43T67DG7L2HVI5CV74ZCM/
[2] https://pci-ids.ucw.cz/read/PC/8086

Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41658
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:16:41 +00:00
Iru Cai 27126f135d cpu/intel/haswell: add Crystal Well CPU IDs
Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:16:29 +00:00
Iru Cai 9c20ad6da2 cpu/intel/common/fsb.c: add Crystal Well support
Without this change, there will be no console output when using a
Crystal Well CPU.

Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS.

Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:16:19 +00:00
Julius Werner 2aedc9776a assert.h: Try to evaluate assertions at compile time
Many places in coreboot seem to like to do things like

 assert(CONFIG(SOME_KCONFIG));

This is somewhat suboptimal since assert() is a runtime check, so you
don't see that this fails until someone actually tries to boot it even
though the compiler is totally aware of it already. We already have the
dead_code() macro to do this better:

 if (CONFIG(SOME_KCONFIG))
   dead_code();

Rather than fixing all these and trying to carefully educate people
about which type of check is more appropriate in what situation, we can
just employ the magic of __builtin_constant_p() to automatically make
the former statement behave like the latter.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I06691b732598eb2a847a17167a1cb92149710916
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-03 05:15:59 +00:00
Julius Werner 3e034b6e9a Change all assert(0) to BUG()
I would like to make assertions evaluate at compile time where possible,
but sometimes people used a literal assert(0) to force an assertion in a
certain code path. We already have BUG() for that so let's just replace
those instances with that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I674e5f8ec7f5fe8b92b1c7c95d9f9202d422ce32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03 05:15:15 +00:00
Julius Werner c435d3daa7 qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32
According to my SC7180 reference manual, these three GPIOs are in the
NORTH TLMM, but our pin table lists them as SOUTH. That means all
accesses our code has been doing to them have just been hitting empty
address space.

BUG=b:160115694

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If9c03ac890a7975855394c2e08b8433472df204d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-08-03 05:13:07 +00:00
Jes Klinke 683ac6f204 lib/string: Add standard strstr() function
Adding implementation of standard library strstr()

See https://review.coreboot.org/c/coreboot/+/43741 for context.

Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-03 05:12:23 +00:00
Alex Levin e968e3762e mb/google/volteer: Change wake to be triggered on a raising edge
ACPI_GPIO_IRQ_EDGE_BOTH sets both edges as wake. The desired behavior is wake on rising edge, change to ACPI_GPIO_INPUT_ACTIVE_LOW.

Fixing for both Volteer and Volteer2 variants.

BUG=b:146083964
BRANCH=None
TEST=tested on a Volteer

Change-Id: I2d3339151bf4e2cbae60aaf97ba1bd7909a2b9a9
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-03 05:11:50 +00:00
Patrick Rudolph 6588652ef5 mb/emulation/qemu-armv7: Fix board
Fix multiple issues allowing to boot until "Payload not loaded":

* The FMAP_CACHE was placed in memory mapped flash
  - Place the FMAP_CACHE in DRAM.
* The FMAP_CACHE was overlapping the BOOTBLOCK, which has a default size
  of 128KiB.
  - Increase the bootblock size in memlayout to 128KiB to match the FMAP.
* The heap in bootblock wasn't usable.
  - Add a linking check in armv7 common bootblock to relocate itself to
    the linked address.
* A FIT payload couldn't be compiled in as the POSTRAM_CBFS_CACHE was
  missing.
  - Add the POSTRAM_CBFS_CACHE to memlayout.
* The coreboot log is spammed with missing timestamp table error messages
  - Add TIMESTAMP table to memlayout.

Tested on QEMU armv7 vexpress.

Change-Id: Ib9357a5c059ca179826c5a7e7616a5c688ec2e95
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03 05:11:17 +00:00
Hung-Te Lin 935495f3e7 mb/google/kukui: indent config names for burnet and esche
The 'burnet' and 'esche' in Kconfig.name should have two spaces
after the arrow.

BUG=None
TEST=make menuconfig
BRANCH=kukui

Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43986
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:10:09 +00:00
Paul Menzel e1574e31f6 Doc/mb/facebook/monolith: Correct grammar by removing plural *s*
Change-Id: I2d14902f9d975e89cd2842f4c12eab8ca4018fbf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:09:50 +00:00
Paul Menzel d3d316a28f Doc/mb/lenovo: Mark up file name as code/monospace
Change-Id: I397b1dc0c3faf65811889d4c5814d6dcca7fe6b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43748
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:08:58 +00:00
Martin Roth 114cf22e8d drivers/amd/i2s_machine_dev: return if scope is NULL
Avoid dereferencing a null pointer.

Found-by: Coverity CID 1430549
BUG=None
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I53f6a38aac6e7f94c3c370996b3b82ca0d88dac4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-03 05:08:39 +00:00
David Wu 6880aec670 mb/google/volteer/var/todor: Support ELAN i2c-hid touchpad
Update ELAN i2c-hid touchpad configuration

BUG=b:160741785
BRANCH=None
TEST=Verify touchpad is working fine.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2549048766d0707666910bd86c46ac9201bf3905
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43998
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:07:58 +00:00
Kevin Chiu a3bd96fe36 mb/google/zork: Add Samsung K4AAG165WA-BCTD SPD
For dirinboz
DRAMID 0x9: K4AAG165WA-BCTD

BUG=b:161579679
BRANCH=master
TEST=build

Change-Id: I28c0d23f96c5b9c975ffead3a1cac66cbda8c293
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-08-03 05:07:06 +00:00
Caveh Jalali 7eaac6cdc1 soc/intel/tigerlake: Invoke PCIe root port swapping
PCIe bus:function specifiers need to be coalesced the same way
functions are coalesced during bus enumeration. Invoke PCIe root port
devicetree update to swap the enabled root port devices with the
disabled devices.

At this point, the TGL pci_devs.h only describes the PCH-LP, so only
the PCH-LP root ports are listed in this patch. We'll need to add
additional PCIe root ports when PCH-H support is added.

BUG=b:162106164
TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is
swapped with the PCIe device 1c.0 corresponding to Root port 1.

Change-Id: I9230de8b1818f3f2115dab923841fd0e7778be62
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-03 05:06:34 +00:00
Sugnan Prabhu S 6d9f243835 drivers/intel/mipi_camera: Add reference counting for shared resources
This change updates the mipi_camera driver to handle shared power
resource between multiple cameras. This is achieved by adding a guard
variable and methods to manipulate the guard variable before calling
the actual platform method which enables or disables the resource.
PowerResource will call these guarded methods to enable or disable the
resource. This protects the shared resource from being enabled or
disabled multiple times while the other camera is using the resource.

Example:
Consider a platform where two cameras are sharing a GPIO resource 0xXX
and both the cameras calls enable and disable guarded methods for this
GPIO. Actual platform disable method for the GPIO is called only after
the last camera using the GPIO calls DSBx method and RESx becomes 0.

Scope (\_SB.PCI0)
{
	Name (RESx, Zero)
	Method (ENBx, 0, Serialized)
	{
		If ((RESx == Zero))
		{
			\_SB.PCI0.STXS (0xXX)
		}

		RESx++
	}

	Method (DSBx, 0, Serialized)
	{
		If ((RESx > Zero))
		{
			RESx--
		}

		If ((RESx == Zero))
		{
			\_SB.PCI0.CTXS (0xXX)
		}
	}
}

Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 03:44:50 +00:00
Felix Held e2f5fb2549 vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
Also document the maximum nuber of lanes for the different platforms.

Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02 16:45:22 +00:00
Angel Pons 13cd145e02 configs: Add a weird config for Asrock B85M Pro4
This config is meant to build-test several options, such as SMMSTORE,
UBSAN, SIL3114 driver, EM100 support, code coverage and debug options.
Please do not try to use it on real hardware. Or maybe do try.

Change-Id: I8bc19a1987b405d5a654276050b00b956acbdf36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43977
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02 13:09:06 +00:00
Angel Pons bdd3d5f3de soc/intel/baytrail/northcluster.c: Clean up comments
Giant commit aee7ab2 (soc/intel/braswell: Clean up) reformatted comments
to follow the coding style, among many other things. This commit updates
some comments on Bay Trail with two objectives: follow the coding style,
and reduce the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Ibe942a20c624e2c74801c8816616ec83851949af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-02 13:08:50 +00:00
Angel Pons c3be055fbe soc/intel/baytrail/sata.c: Fix SATA init sequence
SeaBIOS on Bay Trail would time out when trying to access a SATA drive.
Turns out that there's two mistakes in the SATA initialization sequence:

 - PCI register 0x94 is wrongly cleared with a bitwise-and operation.
 - PCI register 0x9c is instead written to 0x98, clobbering the latter.

After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M.

Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02 12:18:40 +00:00
Mate Kukri e231949b78 soc/intel/baytrail: Add native refcode replacement
- This is a reverse engineered re-implementation of refcode.elf on
	Bay Trail
- Tested on GBYT4, should work everywhere as it's meant to behave
	exactly the same as the binary refcode

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I91977c509022b0078804dc151d27296260e24bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43133
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02 12:07:08 +00:00
Angel Pons 32b93c94e0 soc/intel/baytrail/northcluster.c: Rename variable
Tested with BUILD_TIMELESS=1, Google Ninja does not change.

Change-Id: I7e74f342c0545f8d2a2128de4162581e5dc01e17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02 12:03:40 +00:00
Angel Pons 7bef2eeb8e soc/intel/baytrail/northcluster.c: Tidy up long lines
These now fit in 96 characters.

Tested with BUILD_TIMELESS=1, Google Ninja does not change.

Change-Id: I7e1dc0126fa4d64f75e686d68c4f70f7109c6da0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02 12:03:21 +00:00
Angel Pons 31d6cd7495 soc/intel/braswell/northcluster.c: Tidy up long lines
These now fit in 96 characters.

Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.

Change-Id: I4275c81d22c03c461c184f26367db80b828033a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02 12:03:04 +00:00
Angel Pons 3a713c0060 soc/intel/braswell/northcluster.c: Rename macro
Spell `KiB` with lowercase `i`.

Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.

Change-Id: Ief606686ee3866a7ede75d097feb510418621fe8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-02 12:02:46 +00:00
Subrata Banik 6362de3829 soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated
FSP default UPD for SkipMpInit is set to 0 which refers to run CPU
feature programming on all cores (BSP + APs).

Setting SkipMpInit=1 is not recommended as it will only limit CPU
feature programming on BSP.

TEST=Able to perform CPU feature programming by FSP on all cores
using external MP PPI services.

Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-08-01 06:55:36 +00:00
Subrata Banik 46f8073249 util/ifdtool: Add Alderlake platform support under IFDv2
Change-Id: Ief8ab6ad280d8a2625404c19d57cd2a24f23cf13
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39533
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01 06:55:25 +00:00
Subrata Banik a717e2f896 util/ifdtool: Make JSL platform entry for lock_descriptor
Change-Id: Ia2ddb4eceab29810b22766a0f241ba4b11e79538
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44057
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01 06:54:51 +00:00
Angel Pons f01884e48c sb/intel/lynxpoint/me_9.x.c: Constify string array
Jenkins complains about `const char *` and says it should instead be
changed to `const char *const`. So, change it so that Jenkins is happy.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: Iecd5fecdefdc2effd0114706648747460d0a4a72
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42630
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 23:34:49 +00:00
Angel Pons 028b8e440b nb/intel/haswell: Configure VCs on Egress Port
System BIOS needs to program the Virtual Channel configuration.

Change-Id: Ic8ff17b3a1c4414633a658c60f2c4f7b195e5825
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43821
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 23:33:43 +00:00
Felix Held 42d5294793 vc/amd/fsp/picasso: document DXIO lane number mapping
Haven't found the official documentation for the DXIO lane mapping on
Pollock, so I had to guess that from the working configurations used in
google/dalboz and amd/cereme.

Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 21:05:34 +00:00
Angel Pons 7d6dae6870 lib/ubsan.c: Update error handlers for current toolchain's GCC
Looks like UBSan isn't being build-tested, and the toolchain has been
updated several times since UBSan support was added. Unexpectedly, it
no longer builds when using GCC from the current toolchain version.

To fix this, rename an error handler and add a newly-introduced handler
for `__ubsan_handle_pointer_overflow`, which works like the existing
handlers. A config file to allow build-testing UBSan is added later.

Change-Id: I5980730d8d22fa1d0512846c203004723847cc6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-31 19:53:27 +00:00
Philipp Deppenwiese 5f9f77672d security/intel/txt: Add Intel TXT support
Add TXT ramstage driver:
 * Show startup errors
 * Check for TXT reset
 * Check for Secrets-in-memory
 * Add assembly for GETSEC instruction
 * Check platform state if GETSEC instruction is supported
 * Configure TXT memory regions
 * Lock TXT
 * Protect TSEG using DMA protected regions
 * Place SINIT ACM
 * Print information about ACMs

Extend the `security_clear_dram_request()` function:
 * Clear all DRAM if secrets are in memory

Add a config so that the code gets build-tested. Since BIOS and SINIT
ACM binaries are not available, use the STM binary as a placeholder.

Tested on OCP Wedge100s and Facebook Watson
 * Able to enter a Measured Launch Environment using SINIT ACM and TBOOT
 * Secrets in Memory bit is set on ungraceful shutdown
 * Memory is cleared after ungraceful shutdown

Change-Id: Iaf4be7f016cc12d3971e1e1fe171e6665e44c284
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-31 16:02:54 +00:00
Patrick Rudolph a9eec2cc2f soc/intel/cannonlake: Fix DMAR when no iGPU is present
Don't emit RMRR for the iGPU if it's not present. This is done on
other platforms as well.

Fixes an DMAR error seen in dmesg on platforms without iGPU.

Change-Id: Iafe86e6938a120b707aaae935cb8168f790bb22f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 09:42:16 +00:00
Jonathan Zhang 25ec615408 mb/ocp/deltalake: configure DIMM_MAX
DeltaLake is a single socket server. Its platform design has 1 DIMM
slot per channel. There are 6 DIMM slots.

Configure DIMM_MAX to overwrite SOC default.

Change-Id: I47ecc81452fe59ed59fd3a239ffe329cbc031d7a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44048
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 09:33:33 +00:00
Jonathan Zhang decf7dc4f8 soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE
CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.

It supports DDR4.

Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.

Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 09:33:03 +00:00
Tim Chu 1343bc394b drivers/ipmi/ocp: Add function to support OCP specific ipmi command
Add driver for OCP specific ipmi commands. With this driver, OCP
specific ipmi command can be used after implementing functions here.

TEST=Build with CB:42242 on Delta Lake, select Kconfig option:
IPMI_OCP and add device in devicetree to open this function.

Use ipmi-util in OpenBMC to dump raw data and check if this
function work.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I2efa85978ec4ad3d75f2bd93b4139ef8059127ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43996
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31 09:31:16 +00:00
Morgan Jang 92bcc4f792 mb/ocp/deltalake: Update SMBIOS type 4 -- Processor Information
TEST=Execute "dmidecode -t 4" to check if the processor information is correct for Deltalake platform

Change-Id: I5d075bb297f2e71a2545ab6ad82304a825ed7d19
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-31 09:30:47 +00:00
Angel Pons 879c4de66f nb/intel/x4x/rcven.c: Rename memory barrier function
Use the name of the assembly instruction it uses, mfence.

Change-Id: I98d7926434694a41fb6415bed4276741fa7996af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:50:12 +00:00
Angel Pons 4ea1d166a5 mb/intel/tglrvp/Kconfig: Drop unnecessary choice name
The only reason to use a named choice statement is if you plan on
having the choice statement in multiple places. Since the `TGL_EC`
name is not used anywhere else, we might as well get rid of it.

Change-Id: Ic0bddefd007ef961bbff61fd656475cae78148e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:50:05 +00:00
Angel Pons bea5ce7a4b arch/x86/smbios.c: Split out weak functions
The `smbios.c` file is rather long. To improve navigability, place weak
function definitions on a separate compilation unit.

Change-Id: Idd2a4ba52b6b23aad8fd63e66ffa747d49ea713d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:47:39 +00:00
Angel Pons 9630ced250 arch/x86/smbios.c: Factor out switch-case block
Most of `smbios_fill_dimm_manufacturer_from_id()` is noise. Factor the
switch into its own function to improve readability.

Change-Id: Ia0757c01572709d16589a4ed622ca2d2cb69dda2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:47:17 +00:00
Angel Pons 3c13da7897 arch/x86/smbios.c: Simplify assignment
We can reduce the amount of duplicated code with a ternary operator.

Change-Id: I8be95a62c54749d39e3e8821abd46d9f467a5a49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:47:02 +00:00
Angel Pons bf2f91c87c arch/x86/smbios.c: Clean up cosmetics
Put `__weak` at the beginning of functions and reflow lines to leverage
the increased line width of 96 characters.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I3a5fd2d4344b83e09f89053c083ec80aa297061e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30 22:46:53 +00:00
Patrick Rudolph 42609d807b nb/intel/*: Fill in SMBIOS type 16 on SNB/HSW
Fill in the maximum DRAM capacity and slot count read from CAPID0_A
registers on Sandy Bridge and Haswell.

While the register isn't part of the Core Series datasheet, it can be
found in the corresponding "Intel Open Source Graphics Programmer's
Reference" datasheets.

Note that the values for DDRSZ (maximum allowed memory size per channel)
need to be halved when only one DIMM per channel is supported. On mobile
platforms, all but quad-core processors are subject to this restriction.

Tested on Lenovo X230:
On Linux, verify that `dmidecode -t 16` reports the actual maximum
capacity (16 GiB) instead of the currently-installed capacity (4 GiB) or
the max capacity assuming two DIMMs per channel is possible (32 GiB).

Change-Id: I6e2346de1ffe52e8685276acbdbf25755f4cc162
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-30 22:45:54 +00:00
Patrick Rudolph 5e007808cd smbios: Fix type 17 for Windows 10
The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows
10, returns an error if SMBIOS tables are invalid. Various tools use
this API call and don't operate correctly if this fails. For example,
the "Intel Processor Diagnostic Tool" program is affected.

Windows then guesses the physical memory size by accumulating entries
from the firmware-provided memory map, which results in a total memory
size that is slightly lower than the actual installed memory capacity.

To fix this issue, add the handle to a type 16 entry to all type 17
entries.

Add new fields to struct memory_info and fill them in Intel common code.
Use the introduced variables to fill type 16 in smbios.c and provide
a handle to type 17 entries.

Besides keeping the current behaviour on intel/soc/common platforms, the
type 16 table is also emitted on platforms that don't explicitly fill
it, by using the existing fields of struct memory_info.

Tested on Windows 10:
The GetPhysicallyInstalledSystemMemory API call doesn't return an error
anymore and the installed memory is now being reported as 8192 MiB.

Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-30 22:31:24 +00:00
Matt Papageorge 95c42c3b04 mb/amd,google/mandolin,zork: Set EFS SPI platform config
Set platform defaults for SPI settings in Kconfig for EFS.

BUG=b:158755102
TEST=Build and boot test on Tremblye and Morphius. Verify
values in output image in a hex editor. Measure 1st x86
timestamp, perf improves by over a second.

Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 20:55:26 +00:00
Aaron Durbin 80e2dd8854 mb/google/zork: remove indirection for dxio lane configuration
There was a mix of open coding DXIO logical lane numbers and clkreq
pins. And there are separate macros depending on the baseboard
as well as processor type. Remove the indirection and supply the values
directly in the descriptors.

BUG=b:162423378

Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-30 20:05:55 +00:00