Commit Graph

24113 Commits

Author SHA1 Message Date
Dan Elkouby 3781e1fda9 autoport: add missing PCI IDs
As seen on ASUS P8Z77-V Pro

Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:33:43 +00:00
David Hendricks f8d13d5658 intel/fsp_broadwell_de: Set FSP serial speed to match coreboot's
This makes FSP use the same baud rate as coreboot so that the user can
more easily change it without having to modify the FSP binary.

Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-16 05:57:06 +00:00
Hannah Williams 57d8ccb5f0 soc/intel/apollolake: Fix CPU address bits
APL and GLK have 39 address bits

Change-Id: I9b761492332c545c13a0594d8f5937ca84bc0699
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16 05:04:35 +00:00
Katherine Hsieh 0c557cd983 Revert "mb/google/reef/sand: Override USB2 phy settings"
This reverts commit aef0d6b0a7.

This commit can only pass far-end USB eye diagram but will fail on 
near-end. Confirmed with Intel we should revert it.

Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/25651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-16 02:39:34 +00:00
Aaron Durbin fa529bb940 soc/intel/apollolake: update cache options for glk
On glk there's a 4MiB L2 cache all the time. Take advantage of that
by initializing a 1MiB cache-as-ram area.

BUG=b:72728953

Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25645
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 02:25:28 +00:00
Werner Zeh cee8532ce3 intel/fsp_broadwell_de: Remove buggy code for SMBus clock gating
The pch_smbus_init() function contains code to enable clock gating for
the SMBus controller. Unfortunately this code is buggy and leads to a
hanging system with the latest microcode version.
The hang occurs as follows:
The clock gate register is mapped into RCBA space. After reading the
RCBA address from the LPC device config space no mask is applied to the
value (only bits 31..14 are valid while bit 0 is the enable bit). For
this reason the final address is off by one. The old microcodes at least
allowed this unaligned access to the RCBA space. With the latest
microcode this access leads to CPU hang.

Once this is fixed the next issue occurs: After setting the clock
gating bit for SMBus (bit 5) the SMBus controller disappears from the
PCI bus completely and hence no usage of it is possible anymore.

To fix this issue the clock gating code is completely removed as it was
intentionally meant to enable clock gating on the SMB_CLK line and not
the clock gating on the PCIe interface of the SMBus controller.

This issue is known already and was discussed on the mailinglist:

[coreboot] BDX-DE PCI init fail
https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html

TEST=Boot mc_bdx1 with microcode version M1050663_07000012.

Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25652
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 02:25:06 +00:00
Patrick Rudolph 0b643d2499 nb/intel/sandybridge/peg: Add PEG driver stub
Required for other ACPI generators, like the one used for _ROM.

* Add ACPI code for PEG10/PEG11/PEG12/PEG60 and include it on all platforms.
* Add PCIe driver for PEG. The driver returns ACPI names for ssdt generators.

Needs test on real hardware.

Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22337
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:55:14 +00:00
Martin Roth 70df5d6e43 src/mainboard/kahlee: Turn on keyboard backlight on grunt
Turn on keyboard backlight in romstage to indicate that the system is
booting.

BUG=b:77921345
TEST=Boot grunt, keyboard backlight comes on.

Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25636
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:50:52 +00:00
Martin Roth 2c3e3ef654 soc/amd/stoneyridge: add a romstage hook for mainboards
There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage.  This adds an early call for configuration
and passes along whether the system is currently resuming from S3.

BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.

Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-13 16:50:41 +00:00
Marcello Sylvester Bauer 24231893d6 drivers/uart/pl011.c Add read support
Implement uart_rx_byte

Change-Id: I5a33b3cd4b333fb244bc55747014a301021e25e0
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/25623
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:47:54 +00:00
Mario Scheithauer 0af272c1a9 siemens/mc_apl1: Fix accuracy issue with IDT PMIC
Due to an accuracy issue on IMON in the IDT PMIC, the reported system
power consumption was higher than the actual consumption. To prevent
this problem, a logic must be implemented in mainboard_init(). This logic
consists of slope and offset as constants for Vcc and Vnn, which need
to be programmed by coreboot. This fix compensates for the accuracy
issue.

Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-13 16:46:59 +00:00
Tim Chen 5d27f40418 Revert "mb/google/reef: Override USB2 phy settings"
This reverts commit 70ba1b7e78.

This commit can only pass far-end USB eye diagram but will fail on near-end.
Confirmed with Intel we should revert it.

Change-Id: I6de44d5240393409d9ec5835a9de0c23453300f7
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25630
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:45:47 +00:00
Richard Spiegel 48e074975d mb/google/kahlee: Fix IRQ routing
ACPI interrupt routing file routing.asl is not reflecting AGESA settings to
the NB Interrupt Routing Registers. The AGESA settings are:
Device  self    INTA    INTB    INTC    INTD
GPP 0	23	0	1	2	3
GPP 1	24	8	9	10	11
GPP 2	25	16	17	18	19
GPP 3	26	24	25	26	27
GPP 4	23	3	0	1	2
HDA	none	22	23	20	21
GBIF	none	6	7	4	5

Fix the routing table, considering that NB IOAPIC starts at interrupt 24.

BUG=b:74104946
TEST=Build and boot to a modified grunt board to enable the emmc. Then used
"cat /proc/interrupts" to get active interrupts. Also checked IOAPIC
redirection registers, which are now being programmed.

Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-13 16:44:42 +00:00
Nico Huber 0beb62760d 3rdparty/libgfxinit: Update submodule pointer
Update libgfxinit to current master. Changes include:

* a fix to decode the size stolen memory correctly on pre-SandyBridge
  hardware,
* a PCI id based generation check, obsoleting the old check based
  on PCH audio ids,
* some minor improvements around rarely used DDI ports (D and E), and
* added support for tiled and rotated framebuffers on Skylake+ hardware
  (less interesting for coreboot, I guess?).

TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6
     (Skylake) both with text and linear framebuffers and observed
     FILO's prompt showing up.

Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25453
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:42:48 +00:00
Tim Chen 53af78d4fb Revert "mb/google/coral: add usb2 phy setting override for some variants"
This reverts commit 06e3e1f055.

This commit can only pass far-end USB eye diagram but will fail on near-end.
Confirmed with Intel we should revert it.

Change-Id: Ie987061e27996b0acc8345bf9aadb42d2c940808
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25629
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:42:18 +00:00
Jonathan Neuschäfer 2f4dde6b9e mb/scaleway/tagada: Document what the selected SMBIOS enclosure type means
This makes the Kconfig file more informative to read.

Change-Id: Icdf4184c8db9cfed4863d9e9f3b714d67f44a4bd
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-13 11:14:11 +00:00
Raul E Rangel 99f54a60bf include/memory_info.h: Change serial number field from 5 bytes to 4
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
serial number. dimm_info.serial required a 4 character ascii string with
a null terminator.

This change makes the serial field so it matches the SPD spec.
smbios.c will then translate the byte array into hex and set it on the
smbios table.

There were only two callers that set the serial number:
* haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
  it already matches the new contract.
* amd_late_init.c: Previously copied the last 4 characters. Requires
  decoding the serial number into a byte array.

google/cyan/spd/spd.c: This could be updated to pass the serial number,
but it uses a hard coded spd.bin.

Testing this on grunt, dmidecode now shows the full serial number:
        Serial Number: 00000000

BUG=b:65403853
TEST=tested on grunt

Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-12 15:21:45 +00:00
Shaunak Saha e96df83583 mb/google/octopus: Configure SMI for ESPI
This patch enables EC SMI when ESPI is enabled.

BUG=b:77857802
TEST= SMI is working in depthcharge.

Change-Id: I52726194b8346488e5ad781e78e33c5d286d132f
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25569
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-12 15:18:32 +00:00
Raul E Rangel 1f54e9571e soc/amd: Fix generating SMBIOS Type 17
The converter was setting SMBIOS values when dimm_info expects SPD
values.

dmidecode now shows the following:
Memory Device
        Array Handle: 0x0000
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 8192 MB
        Form Factor: SODIMM
        Set: None
        Locator: Channel-0-DIMM-0
        Bank Locator: BANK 0
        Type: DDR4
        Type Detail: Synchronous
        Speed: 933 MT/s
        Manufacturer: Hynix/Hyundai
        Serial Number: 00000000
        Asset Tag: Not Specified
        Part Number: HMAA51S6AMR6N-UH
        Rank: 1
        Configured Clock Speed: 933 MT/s
        Minimum Voltage: Unknown
        Maximum Voltage: Unknown
        Configured Voltage: Unknown

Example debug output:
AGESA TYPE 17 DMI INFO:
  Handle: 1
  TotalWidth: 64
  DataWidth: 64
  MemorySize: 8192
  DeviceSet: 0
  Speed: 1200
  ManufacturerIdCode: 44416
  Attributes: 1
  ExtSize: 0
  ConfigSpeed: 933
  MemoryType: 0x1a
  FormFactor: 0xd
  DeviceLocator:   DIMM 0
  BankLocator:  CHANNEL A
  SerialNumber(8): ' 00000000'
  PartNumber(20): 'HMAA51S6AMR6N-UH    '
CBMEM_ID_MEMINFO:
  dimm_size: 8192
  ddr_type: 0x1a
  ddr_frequency: 933
  rank_per_dimm: 1
  channel_num: 0
  dimm_num: 0
  bank_locator: 0
  mod_id: 44416
  mod_type: 0x4
  bus_width: 3
  serial: 0x00000000
  module_part_number(18): 'HMAA51S6AMR6N-UH  '

The serial number we get from AGESA (at least on my
board) is always 00000000. I'm assuming this is because the SPD info is
compiled in.

`mosys memory spd print all` is still failing though. I will look into
that next.

BUG=b:65403853
BRANCH=dimm-info
TEST=Test output above

Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 17:21:16 +00:00
Patrick Rudolph d67a4bd5a7 lib/memrange: Introduce method to clone memrange
Add a new method to clone an existing memrange with all of its entries.
Required for new bootmem type LB_MEM_RAM_DONT_OVERLAP.

Change-Id: I64b27bf2611ca310385ef680f030a3e4aa0c2680
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25582
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11 15:11:04 +00:00
Aaron Durbin c578efd9ca mb/google/octopus: enable MRC recovery cache
Enable the recovery cache to speed up recovery flows. Also
enable clearing of the normal mrc cache on recovery forced retrains.

BUG=b:77871444
TEST=went into recovery twice. 2nd time it boots faster.

Change-Id: Idfce42ac835637fa521545fadfedecd65df91d4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-11 14:49:56 +00:00
Furquan Shaikh 0029d2bcf3 mb/google/octopus: Select DRIVERS_SPI_ACPI
This change selects DRIVERS_SPI_ACPI which is required to add SSDT
node for SPI TPM.

BUG=b:75306520
BRANCH=None
TEST=None

Change-Id: I0728062dae017522ba91a4b5cb16acf9f6bf4f28
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11 14:49:49 +00:00
Raul E Rangel 21db6cccd4 src/lib/dimm_info_util.c: Add methods to convert from SMBIOS to SPD
AMD AGESA returns DIMM info in SMBIOS format. dimm_info expects the data
in SPD format. These methods will be used to update amd_late_init.c so
it sets the correct values.

BUG=b:65403853
TEST=Built and booted grunt. Methods are not called in this commit. So
they were tested with the later commit by verifying the output of
dmidecode.

Change-Id: Id9fa98e9aad83dfd0a86f45e18b3c312665dce9b
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-11 14:41:59 +00:00
Jonathan Neuschäfer 73cd7cf0f2 src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts")
Change-Id: I5730259bc6819defc482d31644e1f476679257b2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25588
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11 14:18:35 +00:00
Sathyanarayana Nujella f42c7d9670 mainboard/intel/cannonlake_rvp: include correct SND related DT entries
For cannonlake_rvp, want to support two sound configurations based on
relevant daughter board connected (either of these configurations:
SND_MAX98373_NHLT and SND_MAX98357_DA7219_NHLT).
By default SSDT included all codec entries.
This patch corrects and includes relevant codec entries in SSDT

BUG=None
BRANCH=master
TEST=Verify 'emerge-cnlrvp coreboot' compiles successfully.

Change-Id: I4f9487f3a81ef2d24315f75ec1d34bfab8560224
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/24918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 14:18:18 +00:00
Mario Scheithauer a0437b7563 siemens/mc_apl1: Make DRAM configuration more flexible
By storing the FSP-M DRAM configuration parameter in the hwinfo block,
one becomes more flexible in case of a change of the DRAM type.
The configuration data from hwinfo block is a one-to-one representation
of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and
ending before parameter 'Ch0_Bit_swizzling' (offset 0x88).

Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-11 14:15:07 +00:00
Marshall Dawson 8f031d8234 amd/stoneyridge: Reorder temp mtrr for flash
Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init.  The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores.  The ranges need to be
the correct calculated values and not some temporary setting.

This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit.  MTRRs within a CU are shared
so the AP always stays in sync.

BUG=b:77457944
TEST=run on Kahlee

Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 14:13:56 +00:00
Jonathan Neuschäfer fbc66b9dc0 util/cbfstool: Print all supported architectures
The list of supported architectures in the usage output of cbfstool is
currently hardcoded and outdated.

Use the arch_names array in common.c to provide and up-to-date list.

Change-Id: I3e7ed67c3bfd928b304c314fcc8e1bea35561662
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-11 14:12:00 +00:00
Jonathan Neuschäfer e32cea15c8 util/cbfstool: Print types on stdout
Currently, "cbfstool -h | less" doesn't show any file types under
"TYPEs:". That's because the file types are printed with
print_supported_filetypes, which uses LOG, which prints to stderr.  Use
printf print_supported_filetypes, and thus print to stdout, to make the
usage output more normal.

Change-Id: I800c9205c59383b63a640bc0798a1bd9117b0f99
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-11 14:11:17 +00:00
Mario Scheithauer ba91cd33b6 soc/intel/common/block/cpu: Fix cpu_get_power_max
To avoid rounding errors with the current data types, the formula in
this function must be converted.

Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 14:09:48 +00:00
Martin Roth 79efe52e7d mainboard/google/kahlee: Enable Keyboard backlight for Grunt
Grunt supports a keyboard backlight, so enable the ASL code.

BUG=b:77455525
Test=Boot Grunt, verify that the string 'KBLT' is in the DSDT.

Change-Id: Idf0f23581bcba0b035c126c68fb167274d7c698a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25470
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11 14:08:52 +00:00
Arthur Heymans 68f688896c Revert "model_206ax: Use parallel MP init"
This reverts commit 5fbe788bae.
This commit was submitted without its parent being submitted,
resulting in coreboot not building.

Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-11 11:49:05 +00:00
Arthur Heymans 5fbe788bae model_206ax: Use parallel MP init
This patch adds a few southbridge calls needed for parallel MP init.

Moves the smm_relocate() function to smm/gen1/smi.h, since that is
where this function is defined now.

Tested on Thinkpad X220, shaves of ~30ms on a 2 core, 4 threads CPU.

Change-Id: Iacd7bfedfccbc09057e1b7ca3bd03d44a888871d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23432
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11 09:56:59 +00:00
Shamile Khan e9eb14079c soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.
This is required for clock parameter settings to take effect.

BUG=b:75306520
BRANCH=None
TEST=On Octopus, used a scope to check that spi_clk fed to tpm is
1 MHz

Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 09:31:20 +00:00
Jonathan Neuschäfer bb3a5efaf7 Correct "MTTR" to "MTRR"
The term MTRR has been misspelled in a few places.

Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 09:30:57 +00:00
Jonathan Neuschäfer 2e744e0fa5 cpu/x86/mtrr: Fix broken output ("indexis")
The missing space resulted in the following broken output:

> ERROR: Not enough MTRRs available! MTRR indexis 10 with 10 MTTRs in
total.

Put the string on one line to make it obvious where the spaces should be
and to help users of grep.

Change-Id: Ib9e8109d88c1bf38e7dda3dbf1c8d47fb0d23265
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11 09:30:43 +00:00
Jonathan Neuschäfer 7b37a08b82 arch/riscv: Remove I/O space access functions (outb, etc.)
RISC-V does not have the kind of I/O space that x86 has. Other
architectures tend to leave out these definitions as well.

Change-Id: I7328dae1f1fa4ef8772750244a0b11a3fa5aa88f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-11 09:30:08 +00:00
Daniel Gröber e4dbd368ac drivers/aspeed/Kconfig: Select HAVE_VGA_TEXT_FRAMEBUFFER
This allows VGA output in SeaBIOS to be enabled using the
SEABIOS_VGA_COREBOOT Kconfig option. Currently, it’s impossible to select
the VGA text frame buffer in the Kconfig menu.

I'm not sure why this wasn't enabled in the first place, but
SeaVGABIOS seems to work just fine with this patch.

Tested on KCMA-D8.

Change-Id: Ic924a12fbe89940b5f26d211eb8de6cab0be767a
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/25554
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11 09:29:51 +00:00
Elyes HAOUAS b93f48205a mb/intel/dg43gt/devicetree.cb: Use tabs over spaces
Change-Id: I5d18dfea0b0a33995de805219bda3a73892e5fde
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-11 09:29:03 +00:00
Arthur Heymans ac312c690c soc/intel: Remove superfluous pointers variables
Change-Id: I639be58df358129c1f420cf8d1540edd408859a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 02:19:43 +00:00
Subrata Banik 445368cdde soc/intel/common: Configure all possible GFX DSM memory reserve range
Intel internal graphics preallocated memory size should be selected from
below lists as per Intel FSP UPD header:

0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB,
0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB,
0xFC:52MB, 0xFD:56MB, 0xFE:60MB

This patch ensures that coreboot can report the same preallocated
memory range for intel grapics during memory layout calculation.

Note: Today all existing SoCs(except Cannonlake) are supported under intel
common code block design may not need to use any other values than 0x0-0x05
for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for
early SoC samples and validation requirement. This code block to justify
all differnet possible ranges that FSP may support for a platform.

TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB
and coreboot could able to calculate GFX DSM range accordingly.

Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 02:19:30 +00:00
Subrata Banik f952983b37 drivers/intel/wifi: Add support for Harrison Peak (HrP)
Move all Intel WIFI PCI ids into device/pci_ids.h file.

TEST=HrP module is getting detected during PCI enumeration.

Change-Id: Ia2d15f3f4a68887521ddbb1b99daf9d98cfa5c8b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11 02:19:21 +00:00
Justin TerAvest 0e100f65a0 mb/google/octopus: Capitalize MB part name
This is for consistency with other platforms.

BUG=b:77494826
BRANCH=None
TEST=Sucessfully rebooted, saw updated name in SMBIOS

Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25591
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10 22:08:46 +00:00
Aaron Durbin 24de59702f soc/intel/apollolake: fix SPI input clock speed
On APL and GLK the i2c blocks use 133MHz input clock, but the
SPI blocks use a 100MHz input clock. Fix this so that the proper
target frequencies can be hit on the SPI controllers.

BUG=b:75306520

Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-10 18:08:28 +00:00
Lijian Zhao e09ba47b8b soc/intel/cannonlake: Set Cannonlake I2C clock
Correct Cannonlake I2C clock frequency to 133Mhz that will match the
silicon, Cannonlake have I2C clock force to 133Mhz.

BUG=b:75306520

Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25610
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10 18:08:05 +00:00
Aaron Durbin 551e4be730 soc/intel/common: prepare for lpss clock split
Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.

BUG=b:75306520

Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10 18:07:54 +00:00
Richard Spiegel 6d61db0d2c soc/amd/stoneyridege: Create AP jump structure
As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.

BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.

Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10 17:09:22 +00:00
Richard Spiegel 09a16e6a32 soc/amd: Add "halt this AP" callback to romstage
As part of moving AGESA calls from bootblock to romstage, callback function
AGESA_HALT_THIS_AP must be available at romstage.

BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.

Change-Id: I0992b2de5856881c19191ec4f637168727686524
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25527
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10 16:24:20 +00:00
Richard Spiegel e2f301d34b mainboard: Make OemCustomize.c available at romstage
As part of moving AGESA calls from bootblock to romstage, OemCustomize.c
of all boards using stoneyridge must be available at romstage.

BUG=b:74236170
TEST=Build grunt and kahlee, actual test will be performed at a later patch.

Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25528
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10 16:23:55 +00:00
Jonathan Neuschäfer 8ee93ae267 Documentation: Fix a bunch of typos
Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10 10:50:06 +00:00