Commit Graph

19383 Commits

Author SHA1 Message Date
Elyes HAOUAS 6e8b3c1110 src/northbridge: Improve code formatting
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:08:19 +02:00
Elyes HAOUAS 6b72787d27 src/arch: Improve code formatting
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16434
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
2016-09-12 20:05:30 +02:00
Alexander Couzens c7702536ed Makefile.inc: build ifdtool using its own makefile
Change-Id: I67c73c101b928d104e231064e05d367bf9584730
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16571
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:04:33 +02:00
Alexander Couzens 746b6abea5 ifdtool/Makefile: use static dependencies
The generated dependencies doesn't work when
used together with our main build system.

Change-Id: I93d26858e961d7e275d586a1b8a26b3d33f3bd41
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16572
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:03:28 +02:00
Alexander Couzens d12ea11c01 ifdtool: fix one whitespace format error
Change-Id: I5b1846eb3ef8253695066b315e8a105803390579
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16570
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:01:24 +02:00
Arthur Heymans a761fa5ec9 lenovo/t60: add hda_verb.c
This creates a config for the Lenovo T60 sound card based
on values taken from vendor bios
(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16).
The sound card configuration on the vendor bios is the same
as the one on the Lenovo x60.

It improves the default behavior of the sound card:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker

Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-12 20:00:40 +02:00
Hakim Giydan 43e5b576b9 arch/arm: Add armv7-r configuration
This change adds armv7-r support for all stages.

armv7-r is an ARM processor based on the Cortex-R series.

Currently, there is support for armv7-a and armv7-m and
armv7-a files has been modfied to accommodate armv7-r by
adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants
to src/include/rules.h.

armv7-r exceptions support will added in a later time.

Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15335
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 19:58:43 +02:00
Rizwan Qureshi 06868f8154 kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.

Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:56:09 +02:00
Rizwan Qureshi d2ec56985f vendorcode/skylake: Add FSP header files without any adaptations
Add header files as is from FSP build output.
Move the FSP header files to new location as in apollolake.
Update all the FSP structure references now that they are
typedef'd.

Change-Id: I148bff04c064cf853eccaaaf7a465d0079c46b07
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16517
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:54:25 +02:00
Naresh G Solanki 55eee48b0e driver/fsp2_0: Include stdint header file in api.h
'bool' type is reported undefined due to missing stdint.h inclusion,
Fix it by including the same.

Change-Id: Ib09c121471bd8c490442330a478145a7d1d8855f
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16538
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:53:00 +02:00
Rizwan Qureshi e8c2e83973 arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrr
In the current implementation of postcar_frame_add_mtrr,
if provided size is bigger than the base address alignment,
the alignment is considered as size and covered by the MTRRs
ignoring the specified size.
In this case the callee has to make sure that the provided
size should be smaller or equal to the base address alignment
boundary.

To simplify this, utilize additonal MTRRs to cover the entire
size specified. We reuse the code from cpu/x86/mtrr/mtrr.c.

Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16509
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:52:27 +02:00
Rizwan Qureshi 8453c4f2fb cpu/x86: Move fls() and fms() to mtrr.h
Move the funtion to find most significant bit set(fms)
and function to find least significant bit set(fls) to a common
place. And remove the duplicates.

Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:51:36 +02:00
Rizwan Qureshi b1b44d34e3 arch/x86: Always compile postcar library in romstage
postcar_loader.c has a useful library of funtions for
setting up stack and MTRRs. Make it available in romstage
irrespective of CONFIG_POSTCAR_STAGE for use in stack setup
after Dram init.

The final step of moving the used and max MTRRs on to stack
is moved to a new function, that can be used outside of
postcar phase.

Change-Id: I322b12577d74268d03fe42a9744648763693cddd
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:50:18 +02:00
Venkateswarlu Vinjamuri d2e92e461d mainboard/google/reef: Enable lpss s0ix
This setting enables lpss to power gate in S0ix.

BUG=chrome-os-partner:53876

Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:49:28 +02:00
Venkateswarlu Vinjamuri 6584973bdc mainboard/google/reef: Disable CLKREQ of unused PCIe root ports
1. Removes PCIe blocker for S0ix.
2. Set the correct PCIe root port for wifi/bt on EVT.
3. Turn off CLKREQs of unused PCIe root ports to power gate the IP.

Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:49:08 +02:00
Werner Zeh 91aea428b5 fsp_broadwell_de: Correct access to SIRQ_CNTL register
The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.

Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 06:33:53 +02:00
Idwer Vollering ba349ab12e buildgcc: Quote command substitution
There are shells where the result of a command substitution is subject
to word splitting (e.g. dash when assigning a value inside an export
statement).

Change-Id: I70a5bc124af7ee621da2bdb4777f3eaba8adafbb
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/15820
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-09-11 14:27:42 +02:00
Antonello Dettori f9aac2f4ac southbridge/intel/i82801dx: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82801dx.

Change-Id: Ic08a23f672f8b5e40b837d49a9475d52c728a306
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16485
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:56:34 +02:00
Antonello Dettori 3c6bfaf8ca southbridge/intel/i82801ax: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82801ax.

Change-Id: I46f0cc92e1034f045988b42df7246f5d0c8d24fc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:56:19 +02:00
Antonello Dettori f068a73807 southbridge/intel/i82371eb: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82371eb.

Change-Id: Ie15a656c817a2ffe0f44ee3a89659d138a1bf212
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16483
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:56:04 +02:00
Antonello Dettori 4e1d9f6b23 southbridge/intel/i3100: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i3100.

Change-Id: Ic9616d5135cfb7206e086e51aaf82eb66540c4bb
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16482
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:55:52 +02:00
Antonello Dettori d3b55c1bb5 southbridge/intel/fsp_rangeley: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/fsp_rangeley.

Change-Id: I6665f85c74eb3e37d78f6eecbec977dc21a5ad12
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16481
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:55:38 +02:00
Antonello Dettori 60a6e153b0 northbridge/intel/x4x: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/x4x.

Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16472
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:55:22 +02:00
Antonello Dettori 1004710579 northbridge/intel/i5000: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/i5000.

Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16471
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:55:07 +02:00
Antonello Dettori 7ea0fe5cbf northbridge/intel/e7505: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/e7505.

Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16469
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10 04:54:53 +02:00
Vaibhav Shankar e6a5f608e1 soc/intel/apollolake: Add functions to calculate GPIO address
Provide iosf and GPIO functions for GPIO address
calculation.

BUG=chrome-os-partner:55877

Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16349
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-09 23:51:01 +02:00
Philipp Deppenwiese 6e4204a0d1 util/release: Add support for signed tags and releases
* Add gpg key command-line parameter for signing.
* Add username command-line parameter for secure ssh clone.
* Tag and releases are signed.
* Generates ascii amored signature files.

Change-Id: I41347a85145dd0389e3b69939497fb8543db4996
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/16553
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09 23:39:42 +02:00
Damien Zammit 55a54f662e mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridge
Although the goal was to hide the ME device by disabling
the PCI bridge, the original comment that this bridge was ME related
was a mistake, this bridge is for PEG not for ME.
We still need this PCI bridge "on" to enable pci express graphics
add-on cards.

Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16496
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-09 19:40:34 +02:00
Antonello Dettori 305224f47a northbridge/intel/fsp_rangeley: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/fsp_rangeley.

Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16470
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09 18:54:56 +02:00
Damien Zammit 88af372fe8 nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfaces
Previously the ME PCI interface (HECI) was being reported as present in
the DMAR ACPI table even when ME firmware was missing or the PCI device
was hidden and HECI would be unresponsive.
Now we check via the PCI config space itself to verify if the HECI
is present or not.

Note that this test could fail if ME firmware is present but
HECI is disabled in devicetree, because it would not advertise that the HECI
exists even though there is a running ME.  Perhaps this behaviour is desirable
because in this case you won't see the HECI in the lspci tree anyway.

Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16330
Tested-by: build bot (Jenkins)
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-09 17:11:44 +02:00
Nico Huber 994a4a16a5 edid: Fix a function signature
Change-Id: Id69cecb5cdd21c2d92aca74658f39c790f7b7b01
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/15211
Tested-by: build bot (Jenkins)
2016-09-08 23:19:06 +02:00
Jeremy Compostella 3ab8ce52f9 libpayload: Fix strtok_r
This patch makes strtok_r:
- handle the end of the string
- handle string that contains only delimiters
- do not set ptr outside of str

Change-Id: I49925040d951dffb9c11425334674d8d498821f1
Signed-off-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Reviewed-on: https://review.coreboot.org/16524
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-08 21:11:34 +02:00
Sebastian "Swift Geek" Grzywna 7e516fbb47 intel/gma: Use defines for registers and values in edid.c
This replaces magic values with defines without changing any value.

Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/16339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-08 19:32:17 +02:00
Aaron Durbin e642b2d1d3 mainboard/google/reef: move devicetree to baseboard
Move the current devicetree.cb to be under variants/baseboard.
New variants can provide their own devicetree as needed.

BUG=chrome-os-partner:56677

Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16510
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-08 16:24:33 +02:00
Duncan Laurie 1ca196841a drivers/i2c/tpm: Fix early TPM probe
The early TPM probe was done directly in tis.c ignoring the lower
layer that provides appropriate access to the chip.  Move this into
a tpm_vendor_probe() function so it can use iic_tpm_read() with all
of the built-in delays and semantics instead of calling i2c_readb()
directly from the wrong layer.

This fixes early init failures that were seen with the cr50 i2c tpm
on the reef mainboard.

Change-Id: I9bb3b820d10f6e2ea24c57b90cf0edc813cdc7e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-08 16:24:08 +02:00
Duncan Laurie 7fbdad80fd lib: Enable hexdump in verstage
Enable the hexdump function in verstage as it can be useful there for
debugging I2C and TPM transactions.

Change-Id: If9dc4bcc30964e18ff5d8a98559f6306c0adec6f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16528
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-08 16:24:01 +02:00
Werner Zeh b5026bf9e0 fsp_broadwell_de: Adjust printed address in SPI debug messages
For an unknown reason the printed address in the SPI debug messages is
modified before it is printed by subtracting the constant 0xf020 from
the passed in address.
What I suppose this debug code should do is to print the used register
address within the SPI controller while any parts of this address that
belongs to the SPI base address should be omitted. To fix that remove
the subtraction of 0xf020 and adjust the address mask to 0x3ff so that
only the offset to the registers inside the SPI controller will be
visible in the debug messages.
In addition switch to uint8_t and friends over u8 to sync up with used
types in this file.

Change-Id: I93ba7119873115c7abc80a214cc30363a6930b3b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16500
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-08 06:12:13 +02:00
Martin Roth 3eb65eca69 Kconfig: Add option for microcode filenames
Hardcoding the microcode filenames into the makefiles is great when
the microcode is in the blobs directory.  When the microcode isn't
posted to the blobs directory, we need some method of supplying the
microcode binary into the build.  This can of course be done manually
after the build has completed, as can be done with everything that
we're including in the ROM image.  Instead of making life hard for
everyone though, let's just add a way to specify where the microcode
rom comes from.

BUG=chrome-os-partner:53013

Change-Id: I7c5127234809e8515906efa56c04af6005eecf0b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/16386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-08 00:29:08 +02:00
Kyösti Mälkki e0d7e2690f intel/i82801gx 82801ix: Remove OpRegion of SMBus host
Defining this OpRegion for SMBus controller prevents linux kernel
driver i2c-i801 from registering SMBus under sysfs, with following
error in dmesg:

  ACPI Warning: SystemIO range .. conflicts with OpRegion .. (\_SB.PCI0.SBUS.SMBI)

Solution taken from intel/bd82x6x. Worth noting we do not
define ENABLE_SMBUS_METHODS anywhere currently.

Removed remaining reference to HSTS from GETAC P470.

Change-Id: I7c13d344b0343387681b46019cc5061b1435b46b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16266
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:06:31 +02:00
Arthur Heymans e8cf4ffbee mb/intel/d945gclf: Disable combined mode to fix SATA
Similarly to 2b2f465fcb
"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA"
SATA must function in "plain" mode because it does not work in
"combined" mode.

Tested on d945gclf

Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16319
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:05:23 +02:00
Damien Zammit 93157f6c1c mb/gigabyte/ga-g41m-es2l: Add IRQs for PCI express graphics in ACPI
With this patch and the previous ones in this set,
PCI express graphics is now working.

01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GT218
        [GeForce 210] [10de:0a65] (rev a2) (prog-if 00 [VGA controller])

Change-Id: Ife691fb381e90e7744fe2ac4e20977be53419a14
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16497
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:05:03 +02:00
Stefan Reinauer cbc0416ea7 src/lib: Fix checkpatch warnings
The script checkpatch.pl complains about these files. Fix
the warnings.

Change-Id: I4271cc35bb101447a316a75273cf8a6e95ed62d5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/16011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-07 22:28:00 +02:00
Arthur Heymans 29fc9bb855 commonlib: move DIV_ROUND macros from nvidia/tegra
DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other
architectures. This patch moves them from soc/nvidia/tegra/types.h
to commonlib/include/commonlib/helpers.h .

Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16415
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07 20:52:42 +02:00
Damien Zammit 614ffc60cf nb/intel/x4x: Correct typos in interrupt routing for PEG
Device 1 on secondary bus instead of device 0 was being routed.

Change-Id: I4207938038acf7ff941afd692e90a690d2426a05
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16515
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 19:06:42 +02:00
Damien Zammit a99c64e129 nb/intel/x4x: Turn on PEG graphics in device enable
Change-Id: I389c4630362af1c1bf6d281c9d2b7fc81bea2d5d
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16495
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-07 19:06:20 +02:00
Damien Zammit 523e90f9c7 nb/intel/x4x: Increase MMIO PCI space to 2GiB
This is necessary for PCI express graphics card add-ons,
otherwise the pci allocator cannot fit the mmio for the
add on card into the space it has available and the OS
turns off the card.  Old value was 1GiB.

Change-Id: I606994501b15e636fe209d1ed4b3d3f73b42bf5c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07 19:06:05 +02:00
Damien Zammit 57321db3ca nb/intel/x4x: Fix DMI init
No more hang on DMI init when wait for DMI is re-enabled.
Previously the virtual channel arbitration table was not being
set up in the south/north bridges causing invalid DMI state.

This has been tested on GA-G41M-ES2L with patches following.
An NVIDIA GT218 card was detected by the OS and displayed using
the nouveau driver with no blobs.

Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16491
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-07 19:05:55 +02:00
Martin Roth d4aa2c4348 include/arch/acpi.h: change IVRS efr field to iommu_feature_info
The field that was previously named 'efr' is actually the iommu feature
info field.  The efr field is a 64-bit field that is only present in
type 11h or type 40h headers that follows the iommu feature info field.

Change-Id: I62c158a258d43bf1912fedd63cc31b80321a27c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16508
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07 19:00:32 +02:00
Martin Roth a66df49e15 x86/acpi.c: use #define for IVRS revision field
The revision field was correct, but the comment was wrong. The revision
1 means that the IVRS table only uses fixed length device entries.
Update the field to use the IVRS revision #define.

Change-Id: I4c030b31e3e3f0a402dac36ab69f43d99e131c22
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07 19:00:05 +02:00
Martin Roth b6a77aa720 arch/x86/include: Add #defines for IVRS tables
I/O Virtualization Reporting Structure (IVRS) definitions from:

AMD I/O Virtualization Technology (IOMMU)
Specification 48882—Rev 2.62—February 2015

Change-Id: I4809856eb922cbd9de4a2707cee78dba603af528
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16506
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07 18:59:54 +02:00