Commit Graph

50681 Commits

Author SHA1 Message Date
Elyes Haouas af776d8b66 sb/intel/bd82x6x: Use {read,write}32p
While on it, sort includes.

Change-Id: Iacc858fbad89b54b1f5891c18cd3043b3963d53f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:51:17 +00:00
Elyes Haouas 067642d939 sb/amd/pi/hudson: Use {read,write}16/32p()
Change-Id: Ic8621a18a1b3c299c3d6eb7b4bff39f1ff7d8492
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:48:01 +00:00
Elyes Haouas a361d35b8d nb/intel/pineview: Use read32p()
Change-Id: Ie2b1131d7db4b81bd6eb2df7a5ba8a6e8b54539b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:46:17 +00:00
Elyes Haouas 9a83eae71e nb/intel/haswell: Use {read,write}32p()
Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:45:59 +00:00
Elyes Haouas a2389ef316 nb/intel/x4x: Use read32p()
Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:45:05 +00:00
Elyes Haouas 421f1ee294 nb/intel/e7505: Use read32p()
Change-Id: I78337cf822cfae177b9ef3040641057a84e90e15
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:44:41 +00:00
Elyes Haouas 4b7d4054d9 nb/intel/sandybridge: Use read{8,32}p()
Change-Id: I3bbb2f02a2dc182956deffc554a6b161a93ad963
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:44:26 +00:00
Elyes Haouas 285bf097ab soc/cavium/cn81xx: Use read64p()
Change-Id: Ia79816ccc230d17dd1ce2bde7a185b4d502ad107
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:44:06 +00:00
Fred Reitberger f68bd1273b mb/amd/birman/gpio: Change non-GEvent GPIOs to PAD_INT
Two GPIOs were set as SCI, but are not GEvent capable pins on morgana.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I00dc1b2595c047ce6898b394061d119ac8680755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:43:24 +00:00
Sean Rhodes 5d029bbb90 mb/starlabs/lite/{glk,glkr}: Adjust THERMTRIP GPIO
Modify the configuration of GPIO_74 (PMIC Thermal Trip Point) as
in it's current configuration, it stops the laptop entering S5.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e31f095ff42a03e3ea1496fe67d69b0f1763a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-06 19:30:12 +00:00
Arthur Heymans bc8f859b2d acpi/acpi.c: Add a method to generate IOAPIC DMAR entries from hw
This reads back the ioapic id from hardware.

Change-Id: I214557bbe963d1086f35f96efb1cb47950099eb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70267
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06 17:44:20 +00:00
Arthur Heymans 8a3e2b8364 soc/intel/xeon_sp: Read ioapic configuration from hardware
This is more robust than hardcoding whathever FSP has set up and is a
lot less code.

Change-Id: I6423ddc139d742879d791b054ea082768749c0a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06 17:06:35 +00:00
Fred Reitberger 8a979d92c9 mb/amd/mayan/gpio: Configure mayan GPIOs
Configure mayan GPIOs per schematic 105-D59700-00A Rev 1.00

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I283afc716487fd8fa6d455194c382d87a3e6860b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 17:02:39 +00:00
Kapil Porwal f90ceb4c3c mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN device
DmaProperty must only be present on endpoint devices.

BUG=b:259716145
TEST=TBD

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic5be85c3d13250646867f8c8f5950796ec339551
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06 16:58:05 +00:00
Arthur Heymans a3204f7278 google/veyron: Fix old style function definition
Function definitions without a type a deprecated in all versions of C.

Change-Id: I2efb42e653b0deb56ba6b0c9789764a9cabc552e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70138
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06 16:32:36 +00:00
Elyes Haouas 33e9e44a17 vc/cavium/bdk/libbdk-arch/bdk-numa.c: Fix old-style function definition
Change-Id: Ia56f813933143ef69c97f1b7643693c6eade6abe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-06 16:18:59 +00:00
wanghao11 f38992e608 drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init
Add retry up to 10 seconds maximal in ipmi_get_device_id.
Without this retry, on OCP Craterlake with BMC version v2022.28.1,
there's a chance that ipmi_get_device_id failed then ipmi device
won't be enabled.

Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7
Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-06 15:20:18 +00:00
Michał Kopeć 9c4ae9131c soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable
SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using
a HECI message that needs to be sent before EOP. Make the option
configurable to allow soft ME disable on alderlake.

Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06 15:18:45 +00:00
Arthur Heymans 34a7e66faa util/cbfstool: Add a new mechanism to provide a memory map
This replaces the mechanism with --ext-win-base --ext-win-size with a
more generic mechanism where cbfstool can be provided with an arbitrary
memory map.

This will be useful for AMD platforms with flash sizes larger than 16M
where only the lower 16M half gets memory mapped below 4G. Also on Intel
system the IFD allows for a memory map where the "top of flash" !=
"below 4G". This is for instance the case by default on Intel APL.

TEST: google/brya build for chromeos which used --ext-win-base remains
the same after this change with BUILD_TIMELESS=1.

Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-06 15:09:09 +00:00
Elyes Haouas ee4646e70e nb/intel/sandybridge: Use write32p()
Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-06 15:06:27 +00:00
Harsha B R a5e04af484 src/ec/intel: Create common code for board_id implementation
This patch creates initial common code structure for board_id
implementation for intel rvp platforms. Board_id helps in
identifying the platform with respect to CHROME_EC and INTEL_EC
(Windows_EC). Changes include
1. Create initial board_id.c and board_id.h
2. Modify the Makefile to include src/ec/intel directory

BUG=b:260654043
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06 08:55:57 +00:00
Bora Guvendik a6f6e6a592 vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.12
The headers added are generated as per FSP v3361.12

BUG=b:261159242
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: Id7986017e1256627027a45325238bf29e0c00cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-05 21:10:26 +00:00
Angel Pons 69a8a53005 soc/intel/common/block/uart: Show ACPI UART in OS
Do not hide UARTs in ACPI mode from the OS, as this prevents using them
on at least Windows. Currently, the driver is only used on the Prodrive
Hermes mainboard.

Change-Id: I01bdccff1b11e1862970c924fd5fc7718a2d6ce9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70155
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 16:05:44 +00:00
Sergii Dmytruk 0a89d5237e security/tpm: remove tis_close()
This function was never called from outside of drivers and
src/drivers/pc80/tpm/tis.c was the only one doing it in a questionable
way.

tpm_vendor_cleanup() also isn't needed as one of tis_close() functions
was its only caller.

Change-Id: I9df76adfc21fca9fa1d1af7c40635ec0684ceb0f
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05 14:46:43 +00:00
Elyes Haouas 2393ad0bfb Makefile.inc: Use 'Wold-style-definition'
Warn when a definition is using '()' instead of '(void)'.
Use of ‘()’ is considered an old-style definition in C1x standards,
but probably not in C2x.

Change-Id: I734cfffe3e89996ab13e846cc08e13753f24f742
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05 14:44:27 +00:00
Martin Roth 9fc96407e2 Makefile: Add printall as a NOCOMPILE target
Previously, running "make printall" when there was no .config available,
the system would give an error that printall wasn't a valid target. This
is because it was only in an invalid if clause.  This change adds it to
the other branch of the if clause so it will print out a notice of what
the issue is.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I20670ae875be67ac2edf877c53de4702c4fc7c7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:42:19 +00:00
Martin Roth 5161b2ffa7 util/genbuild: Fix style & shellcheck issues
There shouldn't be any change to functionality here - this should be
strictly cleanup.
- STYLE: Put variables inside braces.
- SHELLCHECK: Instead of 'var= ' to clear a variable, use 'var=""'
- SHELLCHECK: Put commands and command variables inside quotes.
- SHELLCHECK: Don't use variables inside the printf commands.
- OTHER: COREBOOT_BUILD needed a date format when the variables in the
our_date() function were put into quotes.  This format matches the
output of 'LANG="" LC_ALL=C TZ=UTC0 date'

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3303caee5c7a53c9df579e6f48d2c3d075a8c278
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-12-05 14:41:52 +00:00
Martin Roth 8a79a89ec4 util/genbuild_h: Update version calculation
- 'git describe --match [0-9].[0-9]*' was giving me an error, so use
the basic 'git describe' command instead.
- If a .coreboot-version file exists, use that to determine the version.
This fixes the problem for coreboot releases.
- Don't run git for the versions unless it's being built from a valid
git repository.  Use 0.0 as the default version for timeless or unknown.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5fae2f012cc9b9914d8803af8dd58a885358cb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:41:22 +00:00
Angel Pons def3c5ccab soc/intel/tigerlake: Fix setting `HyperThreading`
The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.

Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:38:11 +00:00
Jonathan Zhang a3311b9f0f acpi/acpi.c: update ACPI table revisions
Update SRAT table revision to 3 according to ACPI spec.

Add CEDT table revision according to CXL spec.

Change-Id: Iecc3a9892b0f8093013b2a426749e2ec5c00803b
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-05 14:34:55 +00:00
Fred Reitberger 64bfc675a5 mb/amd/mayan: Improve naming of EC FW
Change the EC FW CBFS filename prefix to a more accurate "ec/"

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic789df11160e3ffe7b7294b11e1fa80e3c3961ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70206
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:32:45 +00:00
Tim Van Patten 868c8873ef google/skyrim/Kconfig: Enable DPTC for Morthal
Enable SOC_AMD_COMMON_BLOCK_ACPI_DPTC for Morthal boards, to enable
support for the low/no battery boot feature.

BUG=b:217911928
TEST=build_packages --board=skyrim chromeos-bootimage --autosetgov

Change-Id: I3eb6bee6601e34420a90f33f8f2c45cf3fe37f9b
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70216
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:32:33 +00:00
Kapil Porwal 65bcb57eea soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSD
BUG=b:259716145
TEST=Verified SSDT on google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70065
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:32:04 +00:00
Fred Reitberger 9b592f70d6 soc/amd/common/block/include/gpio_defs.h: Fix documentation
Fixing documentation of PAD_INT macro and replacing spaces with a tab to
match the rest of the documentation.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I72a2578ce21dd10b3beb65c706440c3379f216d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70281
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-05 14:31:04 +00:00
Kapil Porwal 7543627f1b acpi: Helper functions to add certain _DSD properties
BUG=b:259716145
TEST=Verified SSDT on google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70063
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:30:57 +00:00
Hsuan Ting Chen 06cd7dbe4c commonlib: Add essential comments for ELOG_CROS_DIAG_RESULT
ELOG_CROS_DIAG_RESULT_* codes should be consistent with the enum
definition of enumerated histograms.

Hence add comments based on the requirements of enum histograms in
histogram guidelines.

BUG=b:4047421
TEST=none

Change-Id: I1a1a7c863d5aa9496649f81dc94fd79a6ad482df
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70145
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:28:32 +00:00
Elyes Haouas 7bde4e80be superio/ite/it8772f/chip.h: Use 'bool' when appropriate
Change-Id: I20c3298a920396718f0dc036e57faf8e46b82b2c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70253
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:28:02 +00:00
Elyes Haouas 9180bae9b2 superio/aspeed/ast2400/chip.h: Include <stdbool.h>
Change-Id: Ib4a0d77e7bb4cb52e91a5965cae0a6c7ddc40090
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70254
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:27:45 +00:00
Cliff Huang 0405dbed77 mb/intel/adlrvp: Add RTD3 support for PCIe slot1
Add RTD3 support for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec

BUG=none
BRANCH=firmware-brya-14505.B

TEST=Insert a SD card or NIC AIC on PCIe slot1 and run
'suspend_stress_test -c 1'. The RP8 should not cause suspend issue.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ieb7d207a7ec3763bad3e82522e86a825c1ed00b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70119
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
2022-12-05 14:27:33 +00:00
Fred Reitberger 3b45454329 MAINTAINERS: Add AMD mayan reference board
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I85d4d4fe11f0b579c2327f3d1dfce90229ca9dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05 14:26:46 +00:00
David Wu a874830dcc mb/google/brya: Set power limit values for kano and zydron
Add the RPL CPU power limits to kano and zydron's power limit table.

BUG=b:261127266
BRANCH=brya
TEST="emerge-brya coreboot chromeos-bootimage", flash zydron with
image-zydron.serial.bin and verify zydron boots successfully to kernel.

Change-Id: I369c5d7a9a3db0c3e7184a23b0f159ed715b5a50
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70238
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:26:23 +00:00
Bo-Chen Chen 35693c5028 soc/mediatek/mt8188: Add support for MIPI panel
We need to add DSI and MIPI_TX settings to support MIPI panel.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70184
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:58 +00:00
Bo-Chen Chen bb4c9ca2d6 soc/mediatek: Fix DSI register definition for MT8186
The DSI CMDQ offset of MT8186 is different from previous SoCs.
Therefore, we define two versions for DSI register header files. The v1
is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188.

BUG=b:244208960
TEST=build pass
BRANCH=corsola

Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:37 +00:00
Bo-Chen Chen b1e7adeca1 soc/mediatek/mt8188: Add display data path for MIPI output
For geralt project, we also support MIPI panel as our firmware display.
So add this patch to configure ddp to choose eDP display or MIPI panel
display.

BUG=b:244208960
TEST=test firmware display pass for both eDP and MIPI panel on MT8188
EVB.

Change-Id: I06f38b1889811274588c26e9284da4d502acf38b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:00 +00:00
Arthur Heymans f9679c4287 nb/intel/gm45: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69300
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:23:37 +00:00
Arthur Heymans 31ba9356b8 nb/intel/i945: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69299
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:23:13 +00:00
Arthur Heymans 803029685f nb/intel/x4x: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05 14:22:39 +00:00
Arthur Heymans 98c92570d9 cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:22:12 +00:00
Matt DeVillier 6f573217a0 mb/google/zork: Select VBOOT by default
Zork boards will not boot without PSP verstage/VBOOT, so select it
by default.

Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69763
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:19:56 +00:00
Arthur Heymans 759448893c soc/nvidia/tegra210: Fix flushing SPI fifo
This will avoid clearing the other bits in fifo_status.

Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05 14:19:03 +00:00