Commit Graph

15793 Commits

Author SHA1 Message Date
Yidi Lin 3d7b6069e1 mediatek/mt8173: Add a stub implementation of the MT8173 SoC
BUG=chrome-os-partner:36682
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a
Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292558
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12587
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:08 +01:00
Mary Ruthven f82e8ab697 cbfs_spi: enable CBFS access in early romstage
Currently the CBFS mmap cannot be accessed at the beginning of romstage
because it waits until DRAM is initialized. This change first loads CBFS
into SRAM and then switches to using DRAM as the backing once it is
initialized.

BUG=chromium:210230
BRANCH=none
TEST=confirm that the cbfs can be access at the beginning and end of
romstage on different boards.

Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83
Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796
Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312577
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12586
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:04 +01:00
Jimmy Huang 857829654c arch/arm64: introduce mmu to bootblock and romstage
We need mmu interfaces in these two stages for,
1. bootblock: to support mmu initialization in bootblock
2. romstage: to be able to add dram range to mmu table

BRANCH=none
BUG=none
TEST=build pass

Change-Id: I56dea5f958a48b875579f546ba17a5dd6eaf159c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf72736bda2233f8e0bdd7a8ca3245f1d941ee86
Original-Change-Id: I1e27c0a0a878f7bc0ff8712bee640ec3fd8dbb8b
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292665
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12585
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-12-03 14:16:55 +01:00
Jimmy Huang 9b423a77d1 arch/arm64: add DMA_COHERENT region macros to memlayout
BRANCH=none
BUG=none
TEST=build pass

Change-Id: Ia997ce97ad42234ab020af7bd007d57d7191ee86
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 604ac738e33fdfbaf093989ea13162c8506b9360
Original-Change-Id: I636a1a38d0f5af97926d4446f3edb91a359cce4c
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292551
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12584
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:16:43 +01:00
Daisuke Nojiri 03688ec1da libpayload: get cbfs offset & size for default media from lib_sysinfo
This change revives the path which was made inert by CL:308520. When
media == CBFS_DEFAULT_MEDIA, cbfs_get_file replaces it with a pointer
to a default media. Thus, get_cbfs_range does not set cbfs offset &
size from lib_sysinfo.

BUG=chrome-os-partner:47772
BRANCH=tot
TEST=Tested on Jerry and Glados

Change-Id: I012f7871336dd24b8eada5c96c4d72117921b0d2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 279ba344788b4ba85f500e6cfcca8199af6d0a89
Original-Change-Id: I7f0798881519026a23d0801d0a790332ab878ff0
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313205
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12583
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:16:34 +01:00
Stefan Reinauer 16c7e0f56c cbfstool: Fix checkpatch error
ERROR: code indent should use tabs where possible
+^I                trampoline_len);$

Change-Id: If46f977e2e07d73e6cfd3038912a172236a7e571
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12620
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02 18:43:47 +01:00
Stefan Reinauer 5dda4df424 cbfstool: remove trampoline_start and trampoline_size
It's not needed, so we can remove some extra file mangling, too.

Change-Id: I80d707708e70c07a29653258b4cb6e9cd88d3de3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12508
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02 18:43:23 +01:00
Stefan Reinauer 0316e1a69f cbfstool: autocreate trampoline
Add the code necessary to create the linux trampoline blob.
Don't enforce this for the in-coreboot build or use objcopy
to produce linux_trampoline.o as it is a bit trickier to get
all the details right than I had hoped:
 - you have to know the elf architecture of the host machine
 - you might have to have more tools (xxd, perl, etc) installed

Change-Id: I9b7877c58d90f9fb21d16e0061a31e19fffa2470
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12505
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02 18:43:01 +01:00
Stefan Reinauer cbce4de976 drivers/intel/fsp1_1: Don't hide build related options behind HAVE_FSP_BIN
The right thing to do is to hide them behind PLATFORM_USES_FSP1_1.
The only things that should depend on HAVE_FSP_BIN is the code
that actually adds the file to CBFS, and the path to the file in Kconfig.

Removing the HAVE_FSP_BIN check requires some default values
for two Kconfig variables.

Change-Id: I9b6c3ed0cdfb0e02421d7b98c488a66e39add947
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12465
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-02 18:42:05 +01:00
Timothy Pearson 347234c1ef util/nvramtool: Use correct virtual address when mapping tables
The existing code used a stale pointer from a previously unmapped
region of memory when parsing the coreboot tables.  Use the correct
pointer from the currently mapped memory region when parsing.

Change-Id: Id9a1c70655fe25bc079e5bee55f15adf674694f8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12619
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 17:32:07 +01:00
Patrick Georgi 8cf590fb1b build system: Emit some build output while adding files to CBFS
Change-Id: I167f570957ca7eaf71fc31e1bd84b9bbad0683eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12551
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 17:30:49 +01:00
Patrick Georgi 708226e906 build system: drop one level of indirection
coreboot.pre1 was generated then copied into coreboot.pre, now without
any additional manipulation. Get rid of that extra step.

Change-Id: I138567cadbc2fa1a6b6c988e34bdaae0e92d5554
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12550
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 17:30:41 +01:00
Patrick Georgi 1cab0125cc build system: Add more files through cbfs-files instead of manual rules
verstage, romstage, and payload can be added through infrastructure now.

Change-Id: Ib9e612ae35fb8c0230175f5b8bca1b129f366f4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12549
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 17:30:36 +01:00
Patrick Georgi 67cb6aa6a7 build system: make cbfs-files mechanism spaces-safe
Space is commonly used as separator in make variables, so escape them
as * (which should be reasonably uncommon in file names and cbfstool
options alike to not be a problem).

Change-Id: Ia77b5559841b5eae3aa1c0c0027f2e7fb882ea2f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12548
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 17:30:31 +01:00
Patrick Georgi 99ae578b43 build system: Allow giving additional cbfstool options to cbfs-files-y
This enables adding romstage, verstage, and payload, that may need
additional options (eg. for XIP or for linux initrd arguments) to be
added with the build system infrastructure instead of manual rules.

Change-Id: Ifde4ec3ca4ab436aca9b51a3c2cc478ed493fbfb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12547
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 17:30:28 +01:00
Martin Roth c7b26c381c lippert/frontronner-af & toucan-af: Fix IASL warnings
Not all the paths through the _OSC method returned a value.  According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.

Fixes warnings for both platforms:
dsdt.aml 1143:  Method(_OSC,4)
Warning  3115 -          ^ Not all control paths return a value (_OSC)
dsdt.aml 1143:  Method(_OSC,4)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _OSC)

Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12530
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 16:10:06 +01:00
Martin Roth b6acc3071f kconfig_lint: Fix check_is_enabled for 2 symbols on the same line
The previous code would miss the first of two IS_ENABLED(CONFIG_symbol)
sequences on a line.  This patch saves the rest of the line and loops
to check any other entries on the same line of text.

Change-Id: If4e66d5b393cc5703a502887e18f0ac11adff012
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 16:09:34 +01:00
Martin Roth 7aa3ceaf24 kconfig_lint: Change from '$file at line $line' to $file:$line
Combine the file and line number into a combination that editors
understand when opening files.  This makes it easier to edit the
errors.

Change-Id: Id2fae6a0a2ca8d726b95e252d80ac918f4edbe23
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12561
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 16:09:06 +01:00
Martin Roth d808017760 kconfig_lint: Separate errors from warnings
- Create subroutines for printing warnings and errors
- Change all the existing warning and error routines to use subroutines
- Add new command line options to suppress errors and to print notes

Change-Id: I04893faffca21c5bb7b51be920cca4620dc283c3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12555
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 16:08:39 +01:00
Martin Roth cacbcf4815 coreinfo: use coreboot crosscompiler
Set up coreinfo makefile to use .xcompile and the coreboot 32-bit cross
compiler toolchain.

Restrict to x86_32 gcc compiler.

Tested in QEMU

Change-Id: I1cc180a5eeaf6cb9a36fdcef70a9819d0f459168
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12454
Tested-by: build bot (Jenkins)
Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 16:07:40 +01:00
Patrick Georgi 89b4abdf80 build system: replace files on UPDATE_IMAGE
So far the build system only added files starting with CBFS_PREFIX/ in
the UPDATE_IMAGE configuration, but there are a number of files that
exist in the global namespace (eg. config, revision, but also
cmos_layout.bin).

Now, existing files are removed if necessary.

Change-Id: I977ff85fe18115c84268103be72e91ca854e62a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12581
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
2015-12-02 11:48:14 +01:00
Martin Roth d9c193d8b3 toolchain.inc: Add IASL test as part of coreboot toolchain
Even though coreboot has IASL as part of its toolchain, it was not being
picked up when testing to make sure coreboot is being compiled with
the coreboot toolchain.

This patch adds an iasl test when testing coreboot toolchain.

Change-Id: I5b989869417c3f60057a91842b911855d9528f1b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12543
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-02 02:02:42 +01:00
Martin Roth 335a9b61b3 toolchain.inc: Improve help messages for coreboot toolchain
Show better help text on how to compile the coreboot toolchain or use
an unsupported toolchain.

Change-Id: I64a2159d324d673784669b2464c1a2769b048678
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12557
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-02 02:01:45 +01:00
Damien Zammit 74d165b18d mainboard/intel/d510mo: Add Intel D510MO mainboard
Board uses Pineview native raminit
Board boots from grub to linux kernel

VGA needs work, currently headless machine

Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/10074
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 00:39:03 +01:00
Damien Zammit 149c4c5d01 x86/smm: Initialize SMM on some CPUs one-by-one
We currently race in SMM init on Atom 230 (and potentially
other CPUs). At least on the 230, this leads to a hang on
RSM, likely because both hyperthreads mess around with
SMBASE and other SMM state variables in parallel without
coordination. The same behaviour occurs with Atom D5xx.

Change it so first APs are spun up and sent to sleep, then
BSP initializes SMM, then every CPU, one after another.

Only do this when SERIALIZE_SMM_INITIALIZATION is set.
Set the flag for Atom CPUs.

Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/6311
Tested-by: build bot (Jenkins)
Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-02 00:38:45 +01:00
Damien Zammit 003d15cab4 northbridge/intel/pineview: Add native raminit
Does native ram init for Intel Atom D5xx 8086:a000 northbridge

Tested on Intel D510MO mainboard, board boots linux kernel

- Works fully with both dimms populated (2x2GB), memtest passes 100%
- Almost boots with only one dimm in one of the slots
  (suspect bad memory map with one dimm?)
- Reads garbage with only one dimm in other slot

Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-02 00:26:45 +01:00
Damien Zammit f7060f1d0f northbridge/intel/pineview: Add remaining boilerplate code for northbridge
This patch does *not* include native raminit

Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12430
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-12-02 00:26:36 +01:00
Timothy Pearson 1a38374535 southbridge/amd/sb700: Fix boot hang when AHCI mode disabled
Existence of requested PCI device was not checked when enabling
IDE mode on the SP5100.  Fix incorrect PCI device ID and check
for device existence before attempting setup.

Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12572
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:59:41 +01:00
Timothy Pearson 273384638b cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 links
Decision Feedback Equalization (DFE) is a form of dynamic
link training used to lower the overall error rate within
the coherent fabric.  Enable it on all capable HT links.

Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12072
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01 16:59:01 +01:00
Timothy Pearson f8549e88e2 cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setup
The existing code did not properly detect various link attributes
on Family 10h/15h processors.  With the addition of new HT3- and
IOMMU-specific code, proper detection has become critical to avoid
system deadlocks.

Fix and streamline link attribute detection.

Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:58:25 +01:00
Timothy Pearson 09830faa8d nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUs
The existing code re-used the Family 10h XCS buffer setup on
Family 15h CPUs, which set incorrect values leading to random
system lockups.

Use the Family 15h XCS buffer setup shown in the BKDG.

Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:56:31 +01:00
Timothy Pearson 346fcb2894 cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0
Minor change to be more explicit about the binary state
of the iolink detect variable.

Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12069
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-01 16:33:03 +01:00
Timothy Pearson 93107bebf6 nb/amd/amdfam10: Fix incorrect channel buffer count configuration
The secondary bus number set code incorrectly overwrote the link
buffer settings in F0x[F4,D4,B4,94].  Constrain the secondary
bus number set to the appropriate bits of the registers.

Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12068
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:32:25 +01:00
Timothy Pearson f1436e58d2 mainboard/asus/kgpe-d16: Enable GART by default
Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12067
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01 16:31:47 +01:00
Timothy Pearson 5edc6695f8 nb/amd/mct_ddr3: Add Family 15h tristate enable codes
The Family 15h DRAM initialization did not set up the various
tristate enable codes in the MCT.

Add Family 15h tristate enable setup.  This fixes multiple
DIMMs on a single channel.

Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12060
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01 16:31:02 +01:00
Martin Roth d45a3477b7 amd/pi/00630F01: Drop HT3_SUPPORT
The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented.

This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT)

Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12556
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-01 16:28:07 +01:00
Martin Roth 317b58234a Makefile.inc: make sure .xcompile is removed when building tools
Most of the toolchain build targets already ran clean-for-update, but
there were a few that didn't.  Add the clean to those targets.

Change-Id: I7faad32ac8bb1815e0c58e7d142ca2dbfc877896
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12571
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01 16:27:32 +01:00
Patrick Georgi 6dc8570719 build system: strip quotes from CONFIG_CBFS_PREFIX in a single location
Instead of having to remember to strip the quotes everywhere so that
string comparisons (of which there are a few) match up, do it right at
the beginning.

Fixes building the image with a .config where CONFIG_CBFS_PREFIX
contains quotes.

Change-Id: I4d63341cd9f0bc5e313883ef7b5ca6486190c124
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12578
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-12-01 09:05:07 +01:00
Martin Roth bd88fa0ef6 fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbol
The symbol BAYTRAIL_SMM was never valid (there's no config statment
initializing the symbol), but it was being selected and used
in the code.

Now that SMM is supported in fsp_baytrail, the code it was trying
to switch can be removed, and just set up for SMM.

Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12553
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-11-30 23:52:51 +01:00
Patrick Georgi 4013469c50 build system: add dependencies for SeaBIOS output
Change-Id: I7b9f1574f6d487c0a6e5c9095c25ee973a96fa89
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12577
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-30 21:21:41 +01:00
Timothy Pearson 309303884c nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time
There is no need to continue testing a DCT configuration after
data errors have already been detected; this just wastes time
during boot.

Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12066
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 19:39:31 +01:00
Marcin Wojciechowski 9586dc72db mainboard/intel: Add Little Plains
This adds a new mainboard: Little Plains for Intel's atom c2000
It was based on Mohon Peak board with some minor changes
This board is not available as standalone product
It is a managment board for
Intel Ethernet Multi-host Controller FM10000 Series
The FSP package is available from Intel: https://www.intel.com/fsp

Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: https://review.coreboot.org/12503
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 18:00:50 +01:00
Timothy Pearson b4b298c449 mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz
The CPU <--> CPU HT wiring on this board has only been validated
to 2.6GHz.  While higher frequencies appear to function initially,
and in fact function when only one CPU package is installed, dual
CPU package systems will lock up after around 6 - 12 hours of uptime
due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks.

If applications are not being used that stress the coherent fabric,
then the uptime before hang may be much longer.  Users attempting
to overclock the HT links are advised to "burn in test" the HT links
by running memtester locked to a node with no local memory installed.

Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12064
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30 05:29:47 +01:00
Timothy Pearson 16a3a7515a cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixes
Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12065
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
2015-11-30 05:21:24 +01:00
Timothy Pearson 01b9f8e4c2 nb/amd/mct_ddr3: Use antiphase to better center DQS window
The BKDG recommends the use of an antiphase window detection
algorithm to ensure that the DQS data eye is properly centered.

TEST: Booted both with DIMMs known to move the data eye into the
prior clock phase and DIMMs known to keep the data eye in the
current clock phase.

Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12059
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 05:19:19 +01:00
Martin Roth 323c7db204 bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbol
As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually
existed in the coreboot codebase.  I didn't see anything that it might
have been a typo of.

Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12563
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-11-30 00:35:38 +01:00
Timothy Pearson 4502df12aa nb/amd/mct_ddr3: Fix odd rank data corruption
The odd rank of each DIMM could experience data corruption due to
incorrect DQS training.  Fix the DQS training algorithm by executing
the relevant portions of the training algorithm on the odd ranks.

Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12058
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:38:13 +01:00
Timothy Pearson df499b53c3 nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select error
Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:37:08 +01:00
Timothy Pearson 0eb163d5d3 nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly set
Also fix incorrect Trfc[0-3] value on Family 15h.

Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:36:34 +01:00
Patrick Georgi 2ca8b31ff5 x86/smm: don't hide harmless declarations
Hiding them requires #if CONFIG_HAVE_SMI_HANDLER instead of
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))

Change-Id: Ib874cd98e195ad7437d05be1696004b29bf97a66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12565
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-29 13:06:04 +01:00