Note that IMC must sleep while SPI writes are in progress.
Instead of using these ACPI methods, flashrom currently does
raw IO to achieve the same.
Change-Id: Ifca4e8328c54d1074b4799ddecfece24607214db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18537
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IMC is used on some of the AMD reference designs, so do not
touch them yet.
Change-Id: I6a58ab53d4a800d4c0c2026e50826122ece2c59f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/21190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
IMC is used on some of the AMD reference designs, so do not
touch them yet.
Change-Id: Iae21e0294f0155f07fb4f4348ebc5b3120d50fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Only a few boards are using IMC for the onboard fan control,
so regarding the availability of IMC selection it should be opt-in,
not opt-out. Also, select HUDSON_IMC_ENABLE for Gizmo 2
because Gizmo 2 could use IMC for the onboard fan control.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I3590b13c3b155405d61e373daf1bd82ca8e3bd16
Reviewed-on: https://review.coreboot.org/c/30756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add S25FL208K (ID 0x4014), S25FL132K (ID 0x4016) and S25FL164K (ID 0x4017)
chips in a way similar to S25FL116K (ID 0x4015) chip from the same family.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I9bf7197bbc0d12797c8ed100c673628de9c140f7
Reviewed-on: https://review.coreboot.org/c/30874
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
butterfly is a Sandybridge device, and selecting Ivybridge
breaks libgfxinit currently due to CPU mismatch
Test: build/boot butterfly w/libgfxinit
Change-Id: I1a7f5a3681d21a256834b11b545855c4365f5f78
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30820
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's supposed to be the same device that is passed to the executing
function.
Change-Id: I6cf994390c16e0393c96a2b2e04a36305be88e68
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In these cases we have to expect a NULL pointer because the IGD
device 0:2.0 may be disabled.
The behaviour still differs from using dev_find_slot(), which may
return a disabled device. Though, if you'd try to read its config
space you'd only read garbage (0xff) and in cases where we filled
ACPI data with devicetree information, the information shouldn't
be interpreted by the OS because of the disabled device.
Change-Id: I1bab8fa3a82daca71d03453315cdd69d8951fc24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30879
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Superseeded with DEBUG_CONSOLE_INIT.
For dbgp_print_data() return early and skip reading
registers when dprintk() would not get printed anyways.
Change-Id: Idf470b8572ad992c8d4684a860412d9140f514ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Under normal circumstances no printk() goes through until
console_hw_init() has completed. This is wanted behaviour,
except when you need to debug the setup of one of consoles.
Change-Id: Ifc2bb22bf930009ee229d4461f512ada3018307b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This board is the only user of these ancient chipsets,
so we'll do all in one go.
Also wipe out some extra headers.
Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This was used to check romcc-built bootblock and romstage
agree about the location of 16-bit entrypoint. There was
no need to customize it as bootblock size requirement did
not grow. Just check for a fixed location at 4 GiB - 4 KiB.
With C_ENVIRONMENT_BOOTBLOCK we can have a proper symbol
for the purpose, since it appears in the same compilation
unit. It will adjust if C_ENV_BOOTBLOCK_SIZE changes.
Change-Id: I93f3c37e78ba587455c804de8c57e7e06832a81f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS
is by default GEN1 and ThP has bad synchronization on polarity
inversion. When the root port request for speed change, ThP doesn’t
confirm the request, and both sides are moving to polling after
timeout, hot reset is issued, and then most of the CFG space is
initialized. From the observation, CCC/ECPM/LTR would be reset to
default but CCC/ECPM of root port and end devices have been
reconfigured in pci_scan. The LTR configuration for root port
is still missing.
BUG=B:117618636
BRANCH=None
TEST=Warm/cold reset for 10 times and didn't see unsupported request
related AER error messages & $lspci -vvs 00:1c.0|grep LTR and
ensure LTR+ is presenti & $iotools pci_read32 0 0x1c 0 0x68
and ensure bit10 is set.
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/30486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
With the commit a96e66a (soc/intel: Clean mess around UART_DEBUG), an
adjustment is necessary for this mainboard.
Change-Id: I0fb6288959f8bcb45c4cc93cc132f31a5ab2a5ad
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This way date and version are automatically updated when util/crossgcc
was changed, the version contains the commit ID and we have less churn
on these variables.
Change-Id: I475ba9578a8bb421d7c342d2569d7de7fcf4161d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This reverts commit 6fffd70435.
Doing more tests on the Asus KGPE-D16, it seems to cause a reboot loop
quite often. Therefore, revert the commit.
The problem might be caused by the spinlocks used by `get_option()`, and
which are not used by `read_option()`.
Change-Id: Ic25129aa71c8e8e40a65bb2658de78005766fea8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/30830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The Kconfig declaration for FIXED_UART_FOR_CONSOLE was accidentally
placed inside an `if CONSOLE_SERIAL` in a96e66a (soc/intel: Clean mess
around UART_DEBUG).
TEST=Start a clean config, select intel/leafhill and disable serial
console. Confirm that config can be saved without error.
Change-Id: Ie41687e91af11a13697cbe25938dada2c74b40fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Clearing the EBDA was introduced with b4aaaa "Prepare the BIOS data
areas before device init." which states that the purpose of setting up
these area's is just to make sure they are sane. On the S3 path doing
this is not needed and can even thrash data set up by payloads (mostly
SeaBIOS) that used that memory.
Change-Id: I9c54156bd8247e8a34dec6edc27cfc2d33cde595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards
that support it. Also removing unnecessary IO standby support since we
don't use this pin to wake up the SoC.
BRANCH=octopus
BUG=b:122552125,b:120679547
TEST=CTS tests with changes
Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30788
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCI_ADDR() is tightly coupled with different setup_resource_map()
variants so move the declaration away from global namespace.
In the implementation of setup_resource_map() use the bottom
12 bits as the register mask like the other variants do already.
Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30784
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Purpose of the table is to load initial address maps
on PCI function 0:18.1. Provide a macro of its own so
it is clear no other PCI devfn is accessed here.
Change-Id: Ic146207580a5625c4f6799693157b02422bef00a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
What you see in the table are not the PCI devices
that will be written to. Use a helper MCP55_DEV()
to make you look twice what is actually done.
Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
What you see in the table are not the PCI devices
that will be written to. Use a helper CK804_DEV()
to make you look twice what is actually done.
Change-Id: I0ee244dacd6bbd0a88a5e6a5c634f381b0cf713d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The value get_bus_conf() initialises this value to is
discarded.
Change-Id: I8382861574e6f8ab52839169502a5af7c3742daa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
TCO2_STS_SECOND_TO was renamed to TCO_STS_SECOND_TO but one use
slipped through.
Change-Id: I9e3b1cc5cb2f319db35416edf6cea612d755d40a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30805
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression introduced with commit
ad7674e device: Introduce pcidev_on_root() and friends
Function pci_scan_bus() breaks bus->children link
in the devicetree topology while scanning a bus.
While the scan is in progress, accessing PCI
devices with number higher than what is being probed
was not possible because new pcidev_on_root() relies
on having proper topology present at any time.
Change-Id: I7bb497f7390628dd2f0310b380f199783a888c4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Most boards currently do not use EC firmware from SPI flash in the
IFD, this hides this option by default and shows it only for boards
that need it.
A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to
enable this option for boards that need it.
The following list of boards requiring this was provided by
Lijian Zhao:
1. intel/cannonlake_rvp
2. intel/coffeelake_rvp
3. intel/icelake_rvp
4. google/sarien
5. google/hatch
Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Kukui is going to use ADC#4 as SKU ID, and utilizing EC BoardID as
global board_id (i.e., board revision).
BUG=b:122060615
TEST=make; manually tested on Kukui P1 board.
Change-Id: I7bba368c141a7ba6db11f24b8e8e7158f0fc729e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The ID from ADC on Kukui supports 16 different values and we should list
all voltage values ahead.
BUG=b:80501386
TEST=make; manually verified on Kukui P1
Change-Id: Ic3abe07abfe818ca68e180c262fd431d1167b801
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
From `boardid.h`, the uninitialized ID values should be BOARD_ID_INIT
instead of BOARD_ID_UNKNOWN.
BUG=b:80501386
TEST=make; manually verified on Kukui P1
Change-Id: Ie5267e575e38b92ec64a7317defbd00ee153fa0a
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Was tested with the following:
- 2 DIMM slots
- USB
- Ethernet NIC
- automatic fan control
- Libgfxinit with VGA, DVI (HDMI slot unpopulated)
- PS2 Keyboard
- SATA
- PEG
- S3 resume
What does not work:
- Using the second DIMM slot on a channel
G41 can only handle 2 ranks per channel and on this mainboard 1 rank
per DIMM slot. Supporting this would require too much raminit rework
and is not worth it (at least for me)
Change-Id: I67784038ef929f561b82365f00db70a69c024321
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1) Add a Platform Data Region called SI_PDR which is allocated in the flash
descriptor for this platform
2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile
storage.
3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG
so it is clear they are associated.
4) Move the RW_DIAG region to the start of the RW region so that once we can
re-enable a larger BIOS region this sub-region will be in the uncached area
since it is not accessed on a normal boot.
BUG=b:119435206
TEST=tested on Arcada board to ensure expected regions are present
Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This allows to check if stack overflows the car globals.
Change-Id: I369b2d846f35914facb3e69cc762f7e555271bec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Kyösti Mälkki