The SUPERIO_NUVOTON_NCT6776_COM_A symbol should only be visible if
SUPERIO_NUVOTON_NCT6776 is selected as well.
Change-Id: I9c52d596080360bf3fc25265749ced66ec44f5dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33440
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Like the NCT6776, the NCT6791D has muxed COMA/GPIO8 functions. Since it
requires setting different bits, add a new Kconfig symbol to do it.
Change-Id: I62dc18810026f9b1550da19950f66af605600ec8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.
BUG = N/A
TEST = ASRock D1521D4U
Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on IT8786E-I V0.4.1 datasheet with following remark:
"Please note that the IT8786E-I V0.4.1 is
applicable only to the D version."
Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add more registers and make them optional, so they keep untouched/
their default if omitted.
Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change adds support for the SuperIO chip IT8613E. This chip uses
FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so
it relies on support in common ITE code. LDNs were taken from IT8613E
Preliminary Specification V0.3.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some ITEs have more than 3 independent FAN controller outputs. As the
initial implementation assumed only 3 outputs some registers are not
consequently numbered. This change adds macros for accessing those
registers.
Additionally some chips have SmartGuardian always enabled, without the
option for turning it off. For these chips bits that were responsible
for ON/OFF control are either reserved or have different meaning.
Another Kconfig option is added to disable ON/OFF functionality on
platforms that do not support it.
Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/31616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There was CONFIG_ prefix missing in SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG
option, this patch fixes it.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I52919671569175141560cb73e42344aa1725c112
Reviewed-on: https://review.coreboot.org/c/31674
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Register 0x2a [Bit 1] is a PIN89, PIN90 function select for i2c
Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is spotted using ./util/lint/kconfig_lint
To work around the issue, rename the prefix from `CONFIG_` to `CONF_`.
Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add support for the SuperIO part of IT8528E
* Based on the IT8528E datasheet and tests on vendor firmware
TODO: Add support for accessing EC space, which should be
implemented in src/ec/ instead, as it's a separate logical unit.
No datasheet is publicy available.
Tested on wedge100s.
The serial works under the OS without CONFIG_CONSOLE_SERIAL.
Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The two IO regions of the keyboard controller are 1 byte long, not 8.
Change-Id: I7319ce9f84181759f4dc7b59c0020f3a5dd5dc03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/30958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The IO mask shouldn't contain zeros inside the block of ones.
Change-Id: Icfebbf1d1d88ceef58800339bf899931fdc61ab7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/30954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
0 - S5
1 - S0
2 - previous state
This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.
TEST=Did what-jenkins-does with and without this commit and compared
binaries. Nothing changed for the default configurations.
Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK
bootblocks. It is likely unnecessary to do this in verstage.
This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM.
Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There are no public datasheets for this SuperIO. The results are from probing
the registers manually.
Change-Id: Ie5659533c5f224603f918d17942a7057e6701222
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is no public datasheet available for this SuperIO so the resources are
guessed by looking at other ITE SuperIO's and the register dumps while running
vendor firmware.
The only board with this SuperIO in the tree is the asus m5a88-v. Most of the
devicetree entries would have been invalid here so one should not worry too much
about regressions.
Tested with Foxconn d41s.
Change-Id: I6715c68b3aa9aebf6e292975cbf64ce905b30e8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The existing code for modifying the power state after power loss of the system
only implemented the transitions from power off to either power on or power keep
properly.
Since I don't have a board with this chip, I couldn't test the patch on real
hardware. The two cases described above were tested before the original patch
was merged, so I'd expect this to work.
Change-Id: I3c26a2837e451dbfd3cee82e9beedc0f4a90af03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
