Commit Graph

17176 Commits

Author SHA1 Message Date
Timothy Pearson 4488d7371a nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change
When more than one DIMM is installed on a DCT, only the first DIMM
delay values are scaled to the new memory clock frequency after a
memory clock change during write leveling.

Store the previous memory clock of each DIMM during write leveling
to ensure that every DIMM has its delay values rescaled.

Change-Id: I56e816d3d3256925598219d92783246f5f4ab567
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14479
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-25 19:51:55 +02:00
Timothy Pearson 7501b6c285 board_status/to-wiki: Indicate age of test results by background color
A major issue with the board-status Wiki page is that it shows all
test results equally regardless of age.  As a test result ages it
becomes more likely that the board no longer works peroperly under
coreboot due to code churn.

Visually indicate board-test status "at a glance" by smoothly fading
the background color of the test result from green to yellow as the
test result ages.  This patch sets the full yellow transition to 255
days after test for programming convenience, however the number of
days required to fully "stale" a test result could be modified
relatively easily.

Change-Id: I5a076a6cc17d53fda8e4681e38074fc1f46c0e12
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14457
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2016-04-25 17:17:31 +02:00
Martin Roth 3383a25f91 payloads/Makefile.inc: Add phony targets
Add 'nvramcui' target to make it easier to build and test.
Put both nvramcui & coreinfo targets into .PHONY because they
both exist as directories.

Change-Id: I9cf76785e69f3c8e47fe92f1b1648fd0f7a63c3e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14481
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-25 16:45:26 +02:00
Huimin Zhang 2fb2483d44 Reject duplicate results in board-status.
This is in response to issue #28: board-status should reject duplicate 
uploads. 

Change-Id: Iff99be154b35e8c0f9f05f9470d1c2dcff8510b8
Signed-off-by: Huimin Zhang <thehobn@gmail.com>
Reviewed-on: https://review.coreboot.org/14187
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-24 04:19:13 +02:00
Stefan Reinauer 477a0d69e5 fmaptool: Make sure strings are not destroyed on hdestroy()
On Mac OS X hdestroy seems to overwrite node->name. Hence
duplicate the string before stuffing it into the hash search
table.

Change-Id: Ieac2025f5c960cdb8d509dde7e92ba0dd32644b0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14443
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-22 20:41:34 +02:00
Stefan Reinauer c6400e974e drivers/ricoh: Fully switch to src/drivers/[X]/[Y]/ scheme
The previous commit removed Kconfig, but not Makefile.inc

Change-Id: If46a0a3e253eea9d286d8ab3b1a6ab67ef678ee4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14419
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 20:11:52 +02:00
Lee Leahy 019dbd31be soc/intel/quark: Fix MTRR reads
Remove offset override improperly added in the "Disable the ROM shadow"
patch

TEST=Build and run on Galileo Gen2

Change-Id: I32fb2da48e3769d59a49619539053f9afdf63b04
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14450
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:45:03 +02:00
Lee Leahy 50a8c8c95d soc/intel/quark: Fix uninitialized variable d_variant
Initialize the d_variant variable.

Found-by: CID 1353356 Uninitialized variable

TEST=Build and run on Galileo Gen2

Change-Id: I26fba4e77f91d53b6ff9028669aa0186d3174639
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14338
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:44:41 +02:00
Timothy Pearson 8b9c807d72 Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
After substantial testing it has been determined that it is neither
required nor safe to disable the DRAM MCA during initial startup.

This (mostly) reverts commit c094d99611.
The minor debugging enhancements from that commit were left in place.
Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Config-RAM: 1x Kingston 9965516-483.A00LF
Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14446
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:32:20 +02:00
Timothy Pearson 5a359365b9 nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change
Change-Id: I5056cf885b7063a97c095bfaaf01dd8da777a425
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14447
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:31:42 +02:00
Timothy Pearson 490160140a nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs
Certain RDIMMs have inherently large write levelling delays,
in some cases exceeding 1.5 MEMCLK.  When these DIMMs are
utilized, the phase recovery system requires special handling
due to the resultant offset exceeding the phase recovery reporting
capabilities.

Fix an old error where delays > 1.5 MEMCLK were not being programmed
(gross delay high bit was not in set range), and restore special
delay handling for delays greater than 1.5 MEMCLK.

Also enhance debugging for x4 DIMMs around the affected code.

Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Change-Id: I0fb5454c4d5a9f308cc735597607f095fe9188db
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14441
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:29:22 +02:00
Timothy Pearson b474afdd21 nb/amd/mct_ddr3: Run fence training on each node after memory clock change
The BKDG requires phy fences to be re-trained after a memory clock change.
Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked
 -- without actually following this requirement -- !

Fix the single typo that caused several weeks of delay in putting
servers with Kingston RAM (and others) into production...

Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14445
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:29:01 +02:00
Furquan Shaikh 0b6ff78342 soc/intel/apollolake: Flush L1D to L2 only if loaded segment is in CAR
In program_segment_loaded, flush L1D to L2 only if the address of the
loaded segment lies in the CAR region. Add an assert to ensure that
the loaded segment does not cross CAR boundaries.

Change-Id: Ie43e99299ed82f01518c8a1c1fd2bc64747d0c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14449
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-22 17:27:34 +02:00
Patrick Georgi d255744dba intel/i82801ax: Fix IDE setup console log
Fixes two issues:
1. In (the unlikely) case that dev->chip_info is NULL, the output was
   depending on an unknown value near the start of the address space.
2. Output for the secondary interface actually printed the primary
   interface's configuration.

Change-Id: Id0f499a85e6e2410b4efd63baf7fffb2fcaa3103
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14361
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-22 17:25:19 +02:00
Alexander Couzens ebef00faf6 lint/checkpatch.pl: escape \{ in perl regex to fix warnings
Fix warnings:
Unescaped left brace in regex is deprecated, passed through in regex;
marked by <-- HERE in m/\#\s*define.*do\s{ <-- HERE / at util/lint/checkpatch.pl line 3261.
marked by <-- HERE in m/\(.*\){ <-- HERE / at util/lint/checkpatch.pl line 3750.
marked by <-- HERE in m/do{ <-- HERE / at util/lint/checkpatch.pl line 3751.
marked by <-- HERE in m/^\({ <-- HERE / at util/lint/checkpatch.pl line 4194.

Change-Id: If0c1f07a16df9e6cd1c1393a31af8b8ea6a66b01
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14310
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-22 17:24:17 +02:00
Martin Roth f790672f2d util/lint: Find unsigned variables with no length specified
The coding guidelines say that all objects should have fully
qualified types (unsigned int instead of unsigned).

This script finds violations of that rule.

Steps for the filter:
1) Find all lines in the coreboot tree that have the word 'unsigned'
followed by a space.
2) Exclude directories that aren't in the include list or
are specifically excluded.
3) Exclude files that aren't specifically included.
4) Filter out legimitate uses 'unsigned int' or 'unsigned long' for
example.
5) Filter out lines that begin with '/*' or '*'

Change-Id: I46213c6a168e6aafa29a50af814bf7e0fcd32eb6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14269
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-21 23:13:09 +02:00
Stef van Os c012428291 libpayload: time: split time.h from libpayload.h
Move time functions and prototypes from libpayload.h to time.h.
In a similar manner to other c libary headers, this change makes
porting existing applications to libpayload easier.

Change-Id: I71e27c6dddde6e77e0e9b4d7be7cd5298e03a648
Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com>
Reviewed-on: https://review.coreboot.org/14437
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-21 23:08:52 +02:00
Martin Roth 3a6374c454 lint: Add check for amd & apple mainboard license headers
Change-Id: Idda4b7179e3e7b3f5b70be810b428b0651c1cd67
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 23:07:31 +02:00
Iru Cai 12b641d3df coreinfo: Build libpayload in coreinfo directory
When building libpayload, make the build directory and .config outside
libpayload source directory so it'll not pollute the libpayload source
and cause conflicts with other builds.

Change-Id: Idcfbc7dbe4d52a3559229d8450c3efaafd33b93b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14389
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-21 23:06:41 +02:00
Aaron Durbin a4db050318 lib: add common write_tables() implementation
In order to de-duplicate common patterns implement one write_tables()
function. The new write_tables() replaces all the architecture-specific
ones that were largely copied. The callbacks are put in place to
handle any per-architecture requirements.

Change-Id: Id3d7abdce5b30f5557ccfe1dacff3c58c59f5e2b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14436
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 20:49:05 +02:00
Aaron Durbin 5481c961b2 lib/coreboot_table: add architecture hooks for adding tables
Add a architecture specific function, arch_write_tables(), that
allows an architecture to add its required tables for booting.
This callback helps write_tables() to be de-duplicated.

Change-Id: I805c2f166b1e75942ad28b6e7e1982d64d2d5498
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14435
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 20:48:14 +02:00
Aaron Durbin d4afa938c3 lib/bootmem: allow architecture specific bootmem ranges
A architecture-specific function, named bootmem_arch_add_ranges(),
is added so that each architecture can add entries into the bootmem
memory map. This allows for a common write_tables() implementation
to avoid code duplication.

Change-Id: I834c82eae212869cad8bb02c7abcd9254d120735
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14434
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 20:46:45 +02:00
Aaron Durbin 8984af89b8 lib: add helper for constructing coreboot forwarding table
The x86 architecture needs to add a forwarding table to
the real coreboot table. Provide a helper function to do
this for aligning the architectures on a common
write_tables() implementation.

Change-Id: I9a2875507e6260679874a654ddf97b879222d44e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14433
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 20:44:45 +02:00
Aaron Durbin dcee908921 arch/x86: remove low coreboot table support
In addition to being consistent with all other architectures,
all chipsets support cbmem so the low coreboot table path is
stale and never taken.  Also it's important to note the memory
written in to that low area of memory wasn't automatically
reserved unless that path was taken. To that end remove
low coreboot table support for x86.

Change-Id: Ib96338cf3024e3aa34931c53a7318f40185be34c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 20:44:04 +02:00
Aaron Durbin 86cbfa00d0 arch/x86: clean up write_tables()
There were quite a number of #if/#endif guards in the
write_tables() code. Clean up that function by splitting
up the subcomponents into their own individual functions.
The same ordering and logic is kept maintained.

The changes also benefit the goal of using a common core
write_tables() logic so that other architectures don't
duplicate large swaths of code.

Change-Id: I93f6775d698500f25f72793cbe3fd4eb9d01a20c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14431
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 20:43:01 +02:00
Aaron Durbin 60eb2c2c40 arch: only print cbmem entries in one place
Each arch was calling cbmem_list() in their own write_tables()
function. Consolidate that call and place it in common code
in write_coreboot_table().

Change-Id: If0d4c84e0f8634e5cef6996b2be4a86cc83c95a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14430
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 20:42:20 +02:00
Aaron Durbin a0546da57a arch: use Kconfig variable for coreboot table size
Instead of hard coding a #define in each architecture's
tables.c for the coreboot table size in cbmem use a Kconfig
varible. This aids in aligning on a common write_tables()
implementation instead of duplicating the code for each
architecture.

Change-Id: I09c0f56133606ea62e9a9c4c6b9828bc24dcc668
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14429
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 20:40:40 +02:00
Aaron Durbin 0eb1f1cba9 arch/riscv/tables: remove confusion over write_tables()
Apparently the memo was missed about the write_tables()
signature. Fix the confusion.

Change-Id: I8ef367345dd54584c57e9d5cd8cc3d81ce109fef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14421
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 16:07:39 +02:00
Aaron Durbin f7dca0a275 arch/power8/tables: remove confusion over write_tables()
Apparently the memo was missed about the write_tables()
signature. Fix the confusion.

Change-Id: I63924be47d3507d2d7ed006a553414f4ac60d2f9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14420
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 16:07:30 +02:00
Furquan Shaikh 581c42807d soc/intel/apollolake: Set default memory type to uncacheable
Set the default memory type in MTRRCap register to 0. This ensures
that even if the MTRR Enable bit is set in MTRRCap register, the
default memory type is still uncacheable.

Change-Id: I63e7993f8b65dabbab60e7c1bb8d6d89ef4da9ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14428
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-21 08:24:33 +02:00
Kyösti Mälkki defbdcf3e5 AGESA vendorcode: Fix type mismatch
Fix is required to compile AGESA ramstage without raminit.

Change-Id: I783883fa7a12e8a647aa432535bb990a47257e9b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14416
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-04-21 07:39:13 +02:00
Stefan Reinauer e0383d2ce8 xcompile: support being called from payloads/external/.../.../
Change-Id: Icc1361fdd3a8369c4b442ce5b8807c549519c93a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14387
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 07:34:33 +02:00
Stefan Reinauer 479e31e090 imgtec/pistachio: Fix memlayout ASSERT with new binutils
With binutils 2.26 our memlayout ASSERT for mirrored SRAM regions
gets confused due to the lack of parentheses grouping the expressions.

This fixes the following issue:

    LINK       cbfs/fallback/bootblock.debug
    mipsel-elf-ld.bfd: bootblock and gram_bootblock do not match!
    mipsel-elf-ld.bfd: romstage and kseg0_romstage do not match!

Change-Id: Ib406e229b8a552d9ffc4538b55ee0269bfed62a8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14440
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-04-21 07:16:06 +02:00
Noah Glovsky cc93ce79b1 mainboard/apple: add license headers
Change-Id: Id9487212411e5c237d26eb4e5663135f7d0720d1
Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org>
Reviewed-on: https://review.coreboot.org/14425
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-21 00:07:45 +02:00
Noah Glovsky abe40e0664 mainboard/amd: add license headers
Change-Id: Ida8e81c88b2016d90cc8305edfb199143f859ec2
Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org>
Reviewed-on: https://review.coreboot.org/14422
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-21 00:07:05 +02:00
Stef van Os cccef34155 intel/fsp_broadwell_de: fix SPD CBFS file type
File type for SPD in this soc is defined as CBFS_TYPE_RAW in Makefile,
but CBFS_TYPE_SPD in code.

Causes DDR SPD not to be loaded on memory down.

Tested on Prodrive Technologies Broadwell-D 1548 module:
http://prodrive-technologies.com/amc-ix5-intel-broadwell-de-platform/

Change-Id: I44525b4742b3f93d33f0c5bd9ed642c6fb06f23f
Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com>
Reviewed-on: https://review.coreboot.org/14415
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
2016-04-20 23:37:29 +02:00
Bora Guvendik 57abb998a9 soc/intel/apollolake: add definitions for direct IRQ
Change-Id: Ife26f5cf6a06a1a5bf965bbeed7a740a990e8f7f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-20 19:12:17 +02:00
Zhao, Lijian d8d42c2f5f mainboard/amenia: add the inital files for amenia board
Add amenia board files

Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14352
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 18:51:18 +02:00
Jagadish Krishnamoorthy d68a13a602 soc/intel/apollolake: configure interrupt trigger mode
Provide trigger option to configure APIC, sci, smi, nmi interrupts.

Change-Id: I1b553fb4ed1b43aba62346f5b758f8d082606510
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14353
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 18:50:24 +02:00
Andrey Petrov 60c64325cc vboot: Compile loader in postcar as well
Change-Id: Ide3202fca75c77ccebf17d61d93945ba7834a13b
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14398
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 18:47:11 +02:00
Iru Cai 736aa74faf add nvramcui as a secondary payload
Change-Id: Ie38a358ebd2d040ce32b3eeaeb664c568d4dc51e
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14378
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-04-20 18:42:52 +02:00
Iru Cai e44b407b00 nvramcui: Update Makefile
* use crossgcc to build nvramcui
* build libpayload dependency

Change-Id: Ife3054aeb03b4da0568ad47f96c633460d6c07ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14377
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-20 18:41:37 +02:00
Kyösti Mälkki ae29635876 AGESA vendorcode: Suppress maybe-uninitialized warnings
Compiling libagesa with -O2 would throws error on these.

Change-Id: I04afa42f0ac76677f859ca72f9df2e128762ad3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14413
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-20 15:33:25 +02:00
Kyösti Mälkki 4dcbdb0ab9 AGESA vendorcode: Fix logic error
We have not really hit this error, due the test on AGESA_UNSUPPORTED
above.

Change-Id: I6e7d136a1bb46138cc347225bc4c82cfeaff385d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-20 15:31:46 +02:00
Kyösti Mälkki 318e2ac974 AMD CIMX: Drop unused code
We never define B1_IMAGE or B2_IMAGE. These are about building
CIMx as separate binary modules, while coreboot builds these into
same romstage or ramstage module.

Change-Id: I9cfa3f0bff8332aff4b661d56d0e7b340a992992
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-04-20 15:31:18 +02:00
Alexander Couzens 0793afe913 mb/lenovo/x220: disable ME
The ME hangs, the lspci shows no memory and the linux kernel
tries to request irq 0 twice. After suspend-resume the linux
kernel warns about double used irq.

genirq: Flags mismatch irq 0. 00000080 (mei_me) vs. 00015a00 (timer)
mei_me 0000:00:16.0: request_threaded_irq failed: irq = 0.
dpm_run_callback(): pci_pm_resume+0x0/0xa0 returns -16
PM: Device 0000:00:16.0 failed to resume async: error -16

Change-Id: I56ef66388e58dddcfb858294ba274621c55fbef6
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14309
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-04-20 00:26:06 +02:00
Martin Roth a53958098e crossgcc/Makefile.inc: Update jenkins-build-toolchain
Because the builders have the coreboot cross-compilers in their path,
the XGCCPATH variable needs to be set after building the new toolchain
before it will be used.

- Add $DEST/bin to $PATH if $DEST is set, add the default location
for toolchain builds otherwise.  Because the jenkins build image puts
the tools in the path, we ca
- Add KEEP_SOURCES option to help speed up compilation (Slightly).
- Log .xcompile for verification that the right toolchain was used.
- Verify that test-toolchain passes.

Change-Id: I7c270dab94be7e8f801d527169767018a24986e4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14231
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-20 00:24:47 +02:00
Martin Roth 7fae59b049 MAINTAINERS: Add maintainer for Pineview & x4x chipsets & boards
Change-Id: I3c34f6e69b3760a10e67bdc41c8ef0e629beb881
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14129
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-19 19:25:59 +02:00
Stefan Reinauer f4609f9abf drivers/ricoh: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: I3cf32ec58ba40db11fae3dda6dcb2375002e7cb4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:38:29 +02:00
Stefan Reinauer 56f19818dd drivers/generic: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: Ide0d48405d85ea2e889916f778e1556287651707
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:38:06 +02:00