Commit Graph

18149 Commits

Author SHA1 Message Date
Shaunak Saha 9b4be0fce0 intel/amenia: Add wake-up from lid open
This patch adds support to wake up from S3 on lidopen.
mainboard.asl has the _PRW defined for the wakeup support
in S3.

BUG = chrome-os-partner:53992
TEST = Platform wakes up from S3 on lidopen.

Change-Id: I48b456baf5f7e1c2f28454fa66bb90ad761bb103
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15618
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 21:02:20 +02:00
Andrey Petrov 89e7b49a11 soc/intel/apollolake: Consolidate ISH enabling
Since the Integrated Sensor Hub can be disabled through devicetree.cb
as a PCI device, there is no need for a separate register variable.
Remove handling the register and update mainboards' devicetrees. Also
keep ISH disabled on both Reef and Amenia.

Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15710
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 18:21:54 +02:00
Kane Chen d779605c29 soc/intel/apollolake: Properly disable PCIe root ports
1. The hotplug feature needs to be disabled
   so that pcie root ports will be disabled by fsp
2. Correct PcieRootPortEn mapping.
The correct mapping should be like below
PcieRootPortEn[0] ==>  00:14.0
PcieRootPortEn[1] ==>  00:14.1
PcieRootPortEn[2] ==>  00:13.0
PcieRootPortEn[3] ==>  00:13.1
PcieRootPortEn[4] ==>  00:13.2
PcieRootPortEn[5] ==>  00:13.3

BUG=chrome-os-partner:54288
BRANCH=None
TEST=Checked pcie root port is disabled properly
and make sure pcie ports are coalesced.
Also make sure the device will still be enabled after coalescence
when pcie on function 0 is disabled devicetree

Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/15595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 18:20:54 +02:00
Shaunak Saha 97fc426070 google/reef: Add wake-up from lid open
This patch adds support to wake up from S3 on lidopen.
mainboard.asl has the _PRW defined for the wakeup support
in S3.

BUG = chrome-os-partner:53992
TEST = Reef board wakes up from S3 on lidopen.

Change-Id: Ic3bae26cea0642f98d938b3523d08f5902a1f4b5
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 18:20:35 +02:00
Kyösti Mälkki df6eb79a22 intel/x4x: Do not use scratchpad register for ACPI S3
If S3 support was implemented for this platform later on, use
romstage handoff structure instead.

Change-Id: I03c1e07a7fcc17c27203d0c4e32e3958f2ba5273
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15716
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15 16:57:57 +02:00
Kyösti Mälkki 32a38ee85b intel/pineview: Do not use scratchpad register for ACPI S3
If S3 support was implemented for this platform later on, use
romstage handoff structure instead.

Change-Id: Ib0cf3ad41753baee26354c5ed19294048e7fb533
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15715
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15 16:57:46 +02:00
Kyösti Mälkki cbb23af2da AMD binaryPI: Use common romstage ram stack
Note that no binaryPI board has HAVE_ACPI_RESUME.

Change-Id: I52d0bd7dac86822242400f68f6dc202f02d6e0f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:31:07 +02:00
Kyösti Mälkki f32d5b8b66 AMD binaryPI: Split romstage ram stack
Change-Id: Ibbff1fdb1af247550815532ef12f078229f12321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15467
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:20:21 +02:00
Kyösti Mälkki bd274e1363 AMD binaryPI: Use common ACPI S3 recovery
Note that no binaryPI board has HAVE_ACPI_RESUME.

Change-Id: Ic7d87aa81c75374dd1570cef412a3ca245285d58
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15254
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:19:18 +02:00
Kyösti Mälkki bce9bbdfd4 AGESA: Use common romstage ram stack
Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:18:54 +02:00
Kyösti Mälkki a2a7e981d6 AGESA: Use common ACPI S3 recovery
Change-Id: I8ce91088c5fa1a2d2abc53b23e423939fe759117
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15253
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:18:30 +02:00
Aaron Durbin 3969df875e mainboards/skylake: use common Chrome EC SMI helpers
Reduce duplicate code by using the Chrome EC SMI helper functions.

BUG=chrome-os-partner:54977

Change-Id: Ie83e93db514aa0e12e71d371d7afab34a70797fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15689
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15 08:36:24 +02:00
Aaron Durbin 38613d079d soc/intel/skylake: provide poweroff() implementation
Implement poweroff() by putting the chipset into ACPI S5 state.

BUG=chrome-os-partner:54977

Change-Id: I9288dcee13347a8aa3f822ca3d75148ba2792859
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15688
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:36:12 +02:00
Aaron Durbin 1a75560599 mainboards/apollolake: use common Chrome EC SMI helpers
Reduce duplicate code by using the Chrome EC SMI helper functions.

BUG=chrome-os-partner:54977

Change-Id: Iba2ca7185ad7f0566858ce99f5ad8325ecc243cf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15687
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-07-15 08:35:59 +02:00
Aaron Durbin c2b7779d60 soc/intel/apollolake: provide poweroff() implementation
Implement poweroff() by putting the chipset into ACPI S5 state.

BUG=chrome-os-partner:54977

Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15686
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:35:49 +02:00
Aaron Durbin 996b15c934 ec/google/chromeec: provide common SMI handler helpers
The mainboards which use the Chrome EC duplicate the
same logic in the mainboard smi handler. Provide common
helper functions for those boards to utilize.

BUG=chrome-os-partner:54977

Change-Id: I0d3ad617d211ecbea302114b17ad700b935e24d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:35:29 +02:00
Aaron Durbin b743b1a843 lib: add poweroff() declaration
Add a function to power off the system within the halt.h header.

BUG=chrome-os-partner:54977

Change-Id: I21ca9de38d4ca67c77272031cc20f3f1d015f8fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:35:15 +02:00
Aaron Durbin f1e22d5c39 soc/intel/quark: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I034c083604892a5fa25dff3b50e327e0a885b021
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:34:58 +02:00
Aaron Durbin bf168e740f southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I884da90d24bc41e566a290f4135166d9e0cdf474
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15682
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:34:46 +02:00
Aaron Durbin 648c9ae371 southbridge/intel/fsp_i89xx: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ibf2bc3ae89cb5a013cb1ccc439c906b00bf78d66
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15681
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:34:35 +02:00
Aaron Durbin 4d7a9a5569 southbridge/intel/fsp_rangeley: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ia113672fa3cb740cb193c23fd06181d9ce895ac3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:34:22 +02:00
Aaron Durbin e99194555b southbridge/intel/i82801gx: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I08fb52ca13a4355d95fe31516c43de18d40de140
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15679
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:34:10 +02:00
Aaron Durbin 671909b891 southbridge/intel/i82801dx: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I29918fe70b5e511785ed920d8953de3281694be2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:53 +02:00
Aaron Durbin 78c6843a2b southbridge/intel/ibexpeak: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I65270ddcb612f9c63d7dbb2409e4395f96e10a51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15677
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:39 +02:00
Aaron Durbin da5f5094f0 southbridge/intel/lynxpoint: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I03051c1c1df3e64abeedd6370a440111ade59742
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15676
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:30 +02:00
Aaron Durbin 340898f21a southbridge/intel/bd82x6x: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ie709e5d232c474b41f2ea73d3785a7975d6604ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15675
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:18 +02:00
Aaron Durbin 15e439a72e soc/intel/fsp_baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15674
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:33:03 +02:00
Aaron Durbin 9e6d143a82 soc/intel/broadwell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:32:49 +02:00
Aaron Durbin c159bb0d76 soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Iecd94494cb568b20bdf6649b46a9a9586074bdc7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15672
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: York Yang <york.yang@intel.com>
2016-07-15 08:32:35 +02:00
Aaron Durbin e0a49147a6 soc/intel/skylake: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15671
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:32:22 +02:00
Aaron Durbin 1b6196dec9 soc/intel/braswell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:32:09 +02:00
Aaron Durbin f5cfaa3934 soc/intel/baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15669
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:31:56 +02:00
Aaron Durbin 56db47fe20 soc/intel/common: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I40560b2a65a0cff6808ccdec80e0339786bf8908
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15668
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:31:44 +02:00
Aaron Durbin ed35b7c546 soc/intel/apollolake: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15667
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-15 08:31:33 +02:00
Aaron Durbin 20a588b3de arch/x86: provide common Intel ACPI hardware definitions
In the ACPI specification the PM1 register locations are well
defined, but the sleep type values are hardware specific. That
said, the Intel chipsets have been consistent with the values
they use. Therefore, provide those hardware definitions as well
a helper function for translating the hardware values to the
more high level ACPI sleep values.

BUG=chrome-os-partner:54977

Change-Id: Iaeda082e362de5d440256d05e6885b3388ffbe43
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15666
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-07-15 08:31:21 +02:00
Aaron Durbin 932e09d168 drivers/intel/fsp1_1: align on using ACPI_Sx definitions
The SLEEP_STATE_x definitions in the chipsets utilizing
FSP 1.1. driver have the exact same values as the ACPI_Sx
definitions. The chipsets will be moved over subsequently,
but updating this first allows the per-chipset patches
to be isolated.

BUG=chrome-os-partner:54977

Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15665
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:31:09 +02:00
Aaron Durbin 9fe0ff2f83 mainboards: remove direct acpi_slp_type usage
Use the acpi_is_wakeup_s3() API instead of comparing
a raw value to a global variable. This allows for
easier refactoring.

Change-Id: I2813b5d275cbe700be713272e3a88fdb5759db99
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15690
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-07-15 08:30:53 +02:00
Aaron Durbin 30b0c7adf0 mainboards: align on using ACPI_Sx definitions
The mainboard_smi_sleep() function takes ACPI sleep values
of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure
that whatever hardware PM1 control register values are used
the interface to the mainboard is the same. Move all the
SMI handlers in the mainboard directory to not open code
the literal values 3 and 5 for ACPI_S3 and ACPI_S5.

There were a few notable exceptions where the code was
attempting to use the hardware values and not the common
translated values. The few users of SLEEP_STATE_X were
updated to align with ACPI_SX as those defines are
already equal. The removal of SLEEP_STATE_X defines is
forthcoming in a subsequent patch.

BUG=chrome-os-partner:54977

Change-Id: I76592c9107778cce5995e5af764760453f54dc50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15664
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:30:31 +02:00
Aaron Durbin 95c4344a20 arch/x86: provide common ACPI_Sx constants
Instead of open coding the literal values provide more
semantic symbol to be used. This will allow for aligning
chipset code with this as well to reduce duplication.

BUG=chrome-os-partner:54977

Change-Id: I022bf1eb258f7244f2e5aa2fb72b7b82e1900a5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15663
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-15 08:30:13 +02:00
Aaron Durbin ab1960c08a soc/intel/skylake: don't duplicate setting ACPI sleep state
The ramstage main() in lib/hardwaremain.c has the logic
to set the ACPI sleep state based on romstage_handoff. Thus,
there's no need to do it a second time.

Change-Id: I75172083587c8d4457c1466edb88d400f7ef2dd0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15662
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 08:29:59 +02:00
Aaron Durbin 0dca6490b9 soc/intel/braswell: don't duplicate setting ACPI sleep state
The ramstage main() in lib/hardwaremain.c has the logic
to set the ACPI sleep state based on romstage_handoff. Thus,
there's no need to do it a second time.

Change-Id: I88af301024fd6f868f494a737d2cce14d85f8241
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15661
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15 08:29:49 +02:00
Jonathan Neuschäfer 97dc98658a arch/riscv: Move CBMEM into RAM
CBMEM should be placed at the top of RAM, which can be found by parsing
the configuration string. Configuration string parsing isn't yet
implemented, so I'll hard-code the CBMEM location for now.

Change-Id: If4092d094a856f6783887c062d6682dd13a73b8f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15284
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-15 03:01:02 +02:00
Paul Kocialkowski 580db7fd90 chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections
This fills up the RO_FRID, RW_FWID_A and RW_FWID_B FMAP sections with
the relevant version from KERNELVERSION, padded to the right size and
gap-filled with zeros.

Change-Id: I45c724555f8e41be02b92ef2990bf6710be805c2
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15 00:40:19 +02:00
Lin Huang 0776fcb1b5 rockchip/rk3399: extend romstage range
rk3399 sdram size is 192K, and there still some unused space.
We need more romstage space to include the sdram config, so extend
the romstage range.

BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass

Change-Id: Ib827345fe646e985773e6ce3e98ac3f64317fffb
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 626ab15bb4ebb004d5294b948bbdecc77a72a484
Original-Change-Id: Ib5aa1e1b942cde8d9476773f5a84ac70bb830c80
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/359092
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15660
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 00:38:15 +02:00
Lin Huang a406c2a954 rockchip/rk3399: set kevin rev3 pwm regulator initial value to 0.95v
kevin rev3 pwm regulator ripple is still not great, especially for
center logic. To make sdram at 800MHz stable, raise it to 0.95v.

BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass

Change-Id: If4a15eb7398eea8214cb58422bca7cfb5f4a051a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: d29bc581effb0008eb196685aa22dd65b5d478a5
Original-Change-Id: Ideec9c3ab2f919af732719ed2f6a702068d99c8f
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/359130
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15659
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 00:38:04 +02:00
Daisuke Nojiri 0562783182 Google Mainboards: Increase RO coreboot size on flash
Bitmap images will be moved to CBFS from GBB. This patch adjusts the
flash map accordingly for rambi, samus, peppy, parrot, falco, panther,
auron, and strago.

BUG=chromium:622501
BRANCH=tot
TEST=emerge-{samus,falco} chromeos-bootimage
CQ-DEPEND=CL:354710,CL:355100

Change-Id: I6b59d0fd4cc7929f0de5317650faf17c269c4178
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 201a82311ba539b9b02d546ba331ff5bf73e0edf
Original-Change-Id: I0b82285186540aa27757e312e7bd02957f9962ec
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/355040
Reviewed-on: https://review.coreboot.org/15658
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 00:37:52 +02:00
Derek Basehore 8cb974e83e rockchip/rk3399: Remove empty function in sdram.c
This removes an empty function for sdram training. If it's needed
later, we can always add it back.

BRANCH=none
BUG=none
TEST=build and boot firmware for kevin/gru

Change-Id: Id526ef86cf5044894a1a736cc39f10d32f49c072
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3e93461b96bfadc08bf0b46cf99052d9cdffa422
Original-Change-Id: I6bf77d2f81719c68cd78722c3fe9ae547ea1e79c
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354164
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15657
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 00:37:41 +02:00
Derek Basehore 5282fe62d4 rockchip/rk3399: Change copy_to_reg arg type
This changes the src arg for copy_to_reg to a const u32 * instead of a
u32 * in sdram.c.

BRANCH=none
BUG=none
TEST=emerge-gru coreboot

Change-Id: I80f49258b2f8102f0d988fec85b8038a00e18a34
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e0342e5c0181bf65ae78aa9518b0d6bd6cb1d5ec
Original-Change-Id: I362727f1dbe6726bf3240f9219c394786162a1a0
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354163
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15656
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 00:37:28 +02:00
Derek Basehore f3b3ccfe73 rockchip/rk3399: Directly access variables in sdram.c
This simplifies some of the code with better variable declaractions
which removes a lot of line continuations. Instead of declaring a
pointer to the container of the needed struct or array, this retrieves
a pointer to the struct or array instead.

BRANCH=none
BUG=none
TEST=check that gru and kevin still build and boot properly followed
by running "stressapptest -M 1024 -s 1000" and making sure it passes

Change-Id: I34a9be0f35981c03a6b0c27a870981a5f69cecc0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5c17449fcdfbe83ec75a3a006aaf7393c66006b7
Original-Change-Id: If4e386d4029f17d811fa3ce83e5be89e661a7b11
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354162
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/15655
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 00:37:16 +02:00
Derek Basehore 1dd0bc0f60 rockchip/rk3399: cleanup variables in dram_all_config
This removes a variable that was only used once and makes variable
declarations consistent by moving those only used in one block of code
into that block.

BRANCH=none
BUG=none
TEST=on kevin/gru, run "stressapptest -M 1024 -s 3600"

Change-Id: Iacfc0ffef34a4953cfb304b8cb4975b045aea585
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: a79bbbc83d0f5cccf6bb4ad44ae2239c7f4b45e3
Original-Change-Id: Id0ff0c45189c292ab40e1c4aa27929fb7780e864
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/355667
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15654
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15 00:37:06 +02:00