Commit Graph

46807 Commits

Author SHA1 Message Date
Arthur Heymans 4a3331d93c device/pci_device.c: Return if the scan parameter is invalid
Clang is unhappy about codepath of an invalid parameter because
variables remain unset.

Change-Id: I1ba392a48cf3f81a29d9645e5cf220b122d588af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 00:03:08 +00:00
Igor Bagnucki f0d65213c0 src/console/Kconfig: Add option to disable loglevel prefix
This patch adds an option to disable loglevel prefixes. This patch helps
to achieve clear messages when low loglevel is used and very few
messages are displayed on a terminal. This option also allows to
maintain compatibility with log readers and continuous integration
systems that depend on fixed log content.

If the code contains:
  printk(BIOS_DEBUG, "This is a debug message!\n")
it will show as:
  [DEBUG]  This is a debug message!
but if the Kconfig contains:
  CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
the same message will show up as
  This is a debug message!

Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Change-Id: I911bb601cf1933a4c6498b2ae1e4cb4d4bc85621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30 00:02:34 +00:00
Karthikeyan Ramasubramanian 773876401d mb/google/skyrim: Disable PSP postcodes
ESPI is not initialized in PSP. Hence any attempt to write to port80
causes failure to boot. Disable PSP postcodes for now and re-enable it
later after ESPI is initialized in PSP.

BUG=b:224618411
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-29 23:32:21 +00:00
Karthikeyan Ramasubramanian 4a8bbea154 soc/amd/sabrina: Do not clear Port80 enable bit in ESPI Decode
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.

BUG=b:224618411
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29 22:03:20 +00:00
Jianjun Wang aa751cc371 soc/mediatek: Ensure PERST# deassertion time follows the spec
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. To ensure the 100ms
delay requirement is met, calculate the elapsed time since assertion. If
it is smaller than 100ms, do an extra delay.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the measured PERST# time:
[DEBUG]  mtk_pcie_domain_enable: 432517 us elapsed since assert PERST#
[INFO ]  mtk_pcie_domain_enable: PCIe link up success (17 tries)

And the SSD information in boot log is as follows:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 15:41:50 +00:00
Jianjun Wang 2183484e7a mb/google/cherry: Pre-initialize PCIe at the bootblock stage
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.

Instead of asserting PERST# right before PCIe initialization and waiting
for 100ms, which is currently the only function of 'mtk_pcie_pre_init',
so that the extra 100ms delay in ramstage is avoided.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 15:41:43 +00:00
Jianjun Wang acf16bf4f6 soc/mediatek/mt8195: Add early init support
Add early init support for MT8195 platform.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 15:41:37 +00:00
Jianjun Wang 41faa22c53 soc/mediatek: Add early_init for passing data across stages
Add support for "early_init_data" region, which can be used to store
data initialized in an early stage (such as bootblock), and retrieve it
in later stages (such as ramstage).

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 15:41:30 +00:00
Zheng Bao 3a6ab474e0 amdfwtool: Clear the whole byte of EFS_GEN
Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-29 15:41:20 +00:00
Karthikeyan Ramasubramanian 284831e445 soc/amd/common/block/lpc: Add support to not clear port80 enable
SMU locks up sometimes if the port80 enable bit is cleared in the ESPI
Decode register. Add a config to choose between clearing the entire ESPI
Decode Register vs retaining the port80 enable bit.

BUG=None
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-29 14:43:45 +00:00
John Su 2c3c5898f3 mb/google/brya/var/felwinter: Update GPP_E19 from NF to NC
Configure GPIO according to b:224107199 comment#15.
- GPP_E19 from NF to NC.

BUG=b:224107199
TEST=emerge-brya coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-03-29 14:24:24 +00:00
Rex-BC Chen 6f389722fb soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFO
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8186.
Therefore, we select this configuration to enable it.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63114
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29 14:24:05 +00:00
Rex-BC Chen c69ea24ba8 soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"
The memory initialization reference code didn't support returning
DRAM information in the old platforms, for example MT8192 and MT8195.
So we have to add a new configuration USE_CBMEM_DRAM_INFO to make
sure the common code will try to get DRAM information on new
platforms supporting that.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 14:23:29 +00:00
Zhiyong Tao a7477706a0 soc/mediatek/mt8186: Fix pmif setting for low power mode
The current pmif register setting for low power mode is incorrect,
which is causing suspend failure. The issue of suspend failure is that
SRCLKENA0 will not be pulled down. EC will not be informed AP is
suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode()
to correct the setting.

This implementation is based on chapter 3.7 in MT8186 Functional
Specification.

BUG=b:215639203
TEST=test of suspend and resume pass.

Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-29 14:22:48 +00:00
Subrata Banik 9648106683 Documentation: gpio: Update table as per coreboot guidelines
This patch fixes the table issue in markdown file introduced with commit
5338a16b (Documentation: gpio: Fix table).

BUG=b:211573253, b:211950520

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic4f27f46a9d219098612d8b7747ae26116506fce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-29 13:56:58 +00:00
Trevor Wu 812df72a54 mb/google/cherry: support max98390 audio amp
The Cherry follower projects may choose Max98390 for audio output
so we have to add a new config CHERRY_USE_MAX98390. Also, the
'dojo' device is the first one to use it.

BUG=b:204391159
BRANCH=cherry
TEST=emerge-cherry coreboot
TEST=Verify beep function through CLI in depthcharge successfully

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29 13:56:24 +00:00
Subrata Banik af27ac26b3 soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
This patch moves `pmc_clear_pmcon_sts` function into common code and
remove SoC specific instances.

Accessing PMC GEN_PMCON_A register differs between different Intel
chipsets. Typically, there are two possible ways to perform GEN_PMCON_A
register programming (like `pmc_clear_pmcon_sts()`) as:
1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration
   register.
2. Using MMIO access when GEN_PMCON_A is a memory mapped register.

SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to
perform GEN_PMCON_A register programming using PMC MMIO.

BUG=b:211954778
TEST=Able to build brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeff Daly <jeffd@silicom-usa.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-29 13:56:04 +00:00
Elyes Haouas d58580e003 src/mainboard/starlabs: Remove unused <option.h>
Found using:
diff <(git grep -l '#include <option.h>' -- src/) <(git grep -l 'sanitize_cmos(\|get_uint_option(\|set_uint_option(\|get_uint_option(\|set_uint_option' -- src/) |grep "<"

Change-Id: Ib79dfa73b8a30ae1b1e432318bd42e4e3d845af3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-29 00:36:15 +00:00
Felix Held b16d18158b soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZE
The Sabrina microcode update files are 3200 bytes large and not 5568
like it is the case on Cezanne where this file was originally copied
from.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-03-28 16:01:51 +00:00
Raul E Rangel 96839d183c mb/google/skyrim: Implement mb_set_up_early_espi
This will setup the eSPI GPIOs in bootblock right before eSPI init.

BUG=b:226635441
TEST=build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-28 15:44:39 +00:00
Raul E Rangel cc1426b1cd mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BL
The eSPI CS function only exists on AGPIO30.

We will need to rework all boards to make eSPI function.

I also fixed the comments on the other eSPI pins.

BUG=b:226635441
TEST=Build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-28 15:43:53 +00:00
Arthur Heymans f8daf86282 nb/intel/sandybridge/acpi: Support setting PCI bars above 4G
Although coreboot can allocate resources above 4G, Linux does not
consider those allocation valid when there is no region above 4G in
_CRS and disables the device.

TESTED: x220 with and external GPU via the expresscard slot. Linux
does not touch the BARs allocated above 4G.

Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-03-28 15:28:19 +00:00
Elyes Haouas ec97e0a29d include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values
Regarding JEDEC Standard No. 21-C, Release 30, page 13, DDR4_SPD_72B_SO_RDIMM
and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09.
There is no affected board in coreboot tree.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-28 14:14:27 +00:00
Subrata Banik e4cf3fa36d soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig
This patch uses the FSP event handler feature and updates with coreboot
native debug implementation to unify the debug library between coreboot
and FSP.

BUG=b:225544587
TEST=Able to build and boot Brya with the same FSP debug log before and
with this code changes.

Before:

Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

With this code change:

[SPEW ]  Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ]  Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ]  Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ]  The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ]  Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ]  Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ]  Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-28 12:25:31 +00:00
Subrata Banik 7cb6d72116 soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.

BUG=b:225544587
TEST=Able to build and boot brya. Also, verified the FSP debug log is
exactly same before and with this code change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I665def977faaae45f6f834d75e8456859093ba49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-28 12:25:17 +00:00
John Su 3ecc77722c device/pciexp_device: Set resources for pciexp_hotplug_dummy_ops
Without setting the set_resources field for pciexp_hotplug_dummy_ops,
we will get an error during pciexp_hotplug_dummy.

 [ERROR] NONE missing set_resources

Because the set_resources field is considered mandatory, explicitly set
it as no-op noop_set_resources.

BUG=b:220639445
TEST=emerge-brya coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ifee7479c69cf16025dbd4e3924056ed7f8e253cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63101
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-28 02:28:52 +00:00
Jon Murphy 4dac96d968 mb/google/skyrim: Add DXIO descriptors
Add Skyrim DXIO descriptors using info from AMD and skyrim bouard
shematics.

BUG=b:225179599
TEST=Boots to OS on Skyrim Board

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27 15:35:32 +00:00
Pablo Ceballos 69c3611226 mb/google/hatch/moonbuggy: Update GPIOs
Implement the GPIOs that have been changed from genesis.

- Connect scaler UART on pins C12/C13
- Connect the HDMI redriver I2C on C18/C19
- Connect the iMX8 signals on D1/D2/D3/D21/D22
- Connect the EC interrupt on D14 (same as on scout)
- Connect PCH_TYPEC_UPFB on E15 (same as on genesis)
- Configure as not connected the following unused pins: D23, E11, E12,
  F11 -> F22, H0, H8, H9

BUG=b:200876872
TEST=moonbuggy boots

Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3
Signed-off-by: Pablo Ceballos <pceballos@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-27 15:35:18 +00:00
Paul Menzel 77b1ff0f9d tests/lib: Add space before single line comment termination
Change-Id: I9321391cc06afddff94fbba79f93851b553c74b1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-03-27 15:33:39 +00:00
Frank Wu 599a12b450 mb/google/brya/var/banshee: Add mic mute switch setting
Using the GPP_F22 as mic mute switch based on the latest schematic.

BUG=b:223737606, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The mic_mute event is changed when the mic_mute GPIO pin is switched.
Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0
Event: time 1647939954.639995, -------------- SYN_REPORT ------------
Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1
Event: time 1647939954.648152, -------------- SYN_REPORT ------------

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27 15:33:24 +00:00
Zhuohao Lee b0769db48f mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPO
Currently, we control the GPP_D0 in the flash_fp_mcu in order to
program the component's firmware. If we set this pin to NC, then we
can't control the GPP_D0 output low/high and that make the system fails
to program the component's firmware. This patch sets the GPP_D0 to GPO
to fix it.

BUG=b:204679292
BRANCH=firmware-brya-14505.B
TEST=program the component's firmware

Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27 15:33:04 +00:00
Elyes HAOUAS 879d04bf53 soc/mediatek: Include 'console/console.h' when appropriate
Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/)

Change-Id: I93f930de5a2a477ec4c0d8e5c8c57b25f5e4252c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2022-03-27 15:32:51 +00:00
Elyes HAOUAS 8078e900d1 src/soc/mediatek: Remove unused <console/console.h>
Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"

Change-Id: Ifc85ed8b5660eca11be50fddda0cf32aa1dd611c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-27 15:32:18 +00:00
Elyes HAOUAS 4f5f2e7a44 src: Remove unused <bootmode.h>
Found using:
diff <(git grep -l '#include <bootmode.h>' -- src/) <(git grep -l 'platform_is_resuming\|gfx_set_init_done\|gfx_get_init_done\|display_init_required\|get_ec_is_trusted\|get_lid_switch\|get_wipeout_mode_switch\|clear_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_write_protect_state\|init_bootmode_straps' -- src/) |grep "<"

Change-Id: I2ebd472e0cfc641bd7e465b8d29272fd2f7520a1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-27 15:31:07 +00:00
Amanda Huang 651b765567 mb/google/brya/var/brya0: Replace amp max98357 with max98360
Based on Brya EVT schametic, replace audio amp max98357 with max98360.
Add a new audio FW_CONFIG field to support ALC5682I+MAX98360.

BUG=b:224423056
BRANCH=firmware-brya-14505.B
TEST=dmidecode -t 11

Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27 15:30:06 +00:00
Usha P 4625b58833 mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-N
Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP.

BRANCH:NONE
TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-27 15:29:22 +00:00
Zheng Bao fdd47ef1e6 amdfwtool: Add ISH header support for A/B recovery layout
Image Slot Header (ISH) is a new feature.
The rom layout for A/B recovery with ISH:
EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A
              0x4A -> ISH B -> PSP L2 B -> BIOS L2 B

The newer 55758 will updated about the boot priority and update retry
in ISH header.

Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27 15:24:15 +00:00
Felix Held 5f18bb75fb util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types
Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware
table entries, so add those as a preparation for Sabrina support.

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-27 15:21:21 +00:00
Felix Held b6bb0c88be vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table
Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO
lanes.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27 15:16:17 +00:00
Raul E Rangel e102154a5e include/espi.h: Switch to types.h
We use bool in this file, so switch to using types.h.

BUG=b:226635441
TEST=Build skyrim with DEBUG_ESPI

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I78b579de4e3832dd49a18413bf5d03870e347c91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63092
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27 15:13:31 +00:00
Chun-Jie Chen 3708cb56cb soc/mediatek/mt8195: Update audio and adsp power control
To control I2S in MT8195 for dojo project, we need to enable adsp
power before audio power. Therefore, we need to update bus protection
steps to correct the setting.

TEST=build pass
BUG=b:204391159
BRANCH=cherry

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: I0bcf1ddeebf0d3df0a1d6b22273123be1aaf85a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63106
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27 02:17:16 +00:00
Robert Zieba a6562bd221 mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung parts
Parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special handling. This
commit assigns them exclusive IDs 9 and 11 to facilitate this.

BUG=b:224884904

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-25 20:14:24 +00:00
Arthur Heymans d683bf52e9 vendorcode/amd/pi: Fix building with clang
Change-Id: I82913de07acc13af2f5f2c67853e112fb3c66319
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25 20:13:17 +00:00
Arthur Heymans 2fe012633a amd/cimx/sb800: Fix building with clang
These are all set but unused variable problems.

Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25 20:13:00 +00:00
Subrata Banik 3ba6f8cdf8 drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
This patch implements coreboot native debug handler to manage the FSP
event messages.

`FSP Event Handlers` feature introduced in FSP to generate event
messages to aid in the debugging of firmware issues. This eliminates
the need for FSP to directly write debug messages to the UART and FSP
might not need to know the board related UART port configuration.
Instead FSP signals the bootloader to inform it of a new debug message.
This allows the coreboot to provide board specific methods of reporting
debug messages, example: legacy UART or LPSS UART etc.

This implementation has several advantages as:
1. FSP relies on XIP `DebugLib` driver even while printing FSP-S debug
   messages, hence, without ROM being cached, post `romstage` would
   results into sluggish boot with FSP debug enabled.

   This patch utilities coreboot native debug implementation which is
   XIP during FSP-M and relocatable to DRAM based resource for FSP-S.

2. This patch simplifies the FSP DebugLib implementation and remove the
   need to have serial port library. Instead coreboot `printk` can be
   used for display FSP serial messages. Additionally, unifies the debug
   library between coreboot and FSP.

3. This patch is also useful to get debug prints even with FSP
   non-serial image (refer to `Note` below) as FSP PEIMs are now
   leveraging coreboot debug library instead FSP `NULL` DebugLib
   reference for release build.

4. Can optimize the FSP binary size by removing the DebugLib dependency
   from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary
   size is reduced by ~100KB+ and FSP-S debug library size is also
   reduced by ~300KB+ (FSP-S debug and release binary size is exactly
   same with this code changes). The total savings is ~400KB for each
   FSP copy, and in case of Chrome AP firmware with 3 copies, the total
   savings would be 400KB * 3 = ~1.2MB.

Note: Need to modify FSP source code to remove `MDEPKG_NDEBUG` as
compilation flag for release build and generate FSP binary with non-NULL
FSP debug wrapper module injected (to allow FSP event handler to execute
even with FSP non-serial image) in the final FSP.fd.

BUG=b:225544587
TEST=Able to build and boot brya. Also, verified the FSP debug log is
exactly same before and with this code change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1018e67d70492b18c76531f9e78d3b58fa435cd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-25 20:10:09 +00:00
Arthur Heymans bbf5de55ca sb/amd/hudson/spi.c: Use C over CPP conditional
Change-Id: Ie6e2420813e1b3e8885499b4739b1222aa1b46e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25 20:06:57 +00:00
Arthur Heymans f128adda88 mb/*/BiosCallOuts.c: Fix unused variable
This fixes clang builds.

Change-Id: Ie09fae149a9530ad45f0cd5945e73f46484ef385
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25 20:06:23 +00:00
Arthur Heymans ee1641f066 soc/amd/pi: Use -Wno-pragma-pack
Agesa headers extensively use and override pragma pack which fails to
compile with clang.

Change-Id: Ib234be536388f41d63c2d26cac4c35881af25930
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25 20:06:04 +00:00
Arthur Heymans 457785b820 soc/amd/pi/amd_late_init.c: Fix implicit enum conversion
This fixes building with clang.

Change-Id: Ifda9be8996703b06fe9ee30ffb5f56a91629e065
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25 20:05:50 +00:00
Arthur Heymans 99eab34b9e amd/fam*/northbridge.c: Remove unused reset_memhole variable
Change-Id: I9231e0399d0b3ac6a608282571fc6d4aefad9dfb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25 20:02:56 +00:00