The Intel i3100 northbridge code is the only user of
cache_ramstage(). Therefore, place it next to the sole
consumer.
Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14097
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add all the default options with:
for i in configs/*
do
cp $i .config
make savedefconfig
mv defconfig $i
done
This also switches to minimal config files instead of the full
configuration files that were previously checked in.
Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14077
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
make_idb.py only support RK3288 before, add chip parameter, so we can
support RK3399 either.
Change-Id: I6811acb7f0cdaf1930af9942a70db54765d544d5
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/13913
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes
IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get
their logic reset over pltrst and hence configuring PADRSTCFG to
PLTRST to prevent IRQ strom after S3 resume.
BRANCH=glados
BUG=chrome-os-partner:50536
TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed
after S3 resume.
Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68
Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329453
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331174
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This includes a fix that allows using cbootimage with paths containing
the "@" sign, which happens sometimes in jenkins configurations.
Change-Id: I83154afa35b6d24449e713e57031b1a93d7ac748
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14090
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sort out some style issues that were identified by Paul.
Change-Id: I9ed946ae613c87234f8c9824eb14b8d28909dfcf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14064
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When using PDcurses over a serial line, the background of
coreinfo is not properly cleared. Hence use tinycurses, which
was the only option when coreinfo was developed.
Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14067
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
The two external USB ports and the internal USB header have overcurrent
protection chips with the low-active overcurrent signal connected to the
chipset.
The power-on default for this register disables the software detection
of overcurrent conditions.
After setting the register Linux correctly shows the overcurrent
condition in the kernel log (tested by shorting the 5v and gnd lines on
J14 / the internal USB header):
[ 2015.229921] usb usb1-port3: over-current condition
[ 2015.449925] usb usb1-port4: over-current condition
Simlar for the external ports:
[ 256.237916] usb usb1-port1: over-current condition
[ 256.458084] usb usb1-port5: over-current condition
Note that each signal is shared between two ports:
usboc0#: External ports (port1/5)
usboc1#: Internal ports (port3/4)
Change-Id: I02d498053b8ec61dc206e74a96c4a1dcfd4fae92
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/14084
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix for the T4xx and T5xx series.
It does not apply to X2xx/X6x series as those have only
one GPU, which is always connected to the display.
The T6x series needs special care not handled with this patch.
Without ONBOARD_VGA_IS_PRIMARY the onboard GPU would be
deactivated in case a dedicated GPU is found and active,
leaving the system without a working display.
Change-Id: I94d1700e9afb75de83a4f2ed1ff53ba3b0559ae1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14031
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
BRANCH=none
BUG=chrome-os-partner:49229
BUG=chrome-os-partner:50806
TEST=power on to kernel on Oak Rev3 with 4GB dram
Change-Id: I32fa881df12eb9b7f66086904aebde3dd1483fbf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275
Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331811
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14089
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
If the system is using 4GB of memory, enable 4GB mode in
the memory controller.
Change-Id: I4d0f8ad8d43ff45dd786f4244b11c0879d2088cd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275
Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331811
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14088
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This pin is not used anymore since Rev5.
BRANCH=none
BUG=chrome-os-partner:49375
TEST=make and boot on Rev4/5
Change-Id: I3c775eb2b5e05256523bfd8be814e516944a2f90
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a87e3babe28413bd879a2d95d4612a5b6b541419
Original-Change-Id: I87972ff8961309ecdad03639e1b6fac1da119cd7
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331810
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14087
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add a few additional macros that can be used throughout the coreboot
makefiles.
tolower: returns the value in all lowercase
toupper: returns the value in all uppercase
ws_to_under: returns the value with any whitespace changed to underscores
Change-Id: Icd0e6586481d8f229af0e899e0c94ef7c5c672c3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14093
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For CHROMEOS builds, depthcharge can be built automatically.
This dependency exists because depthcharge without vboot and subsequent
signing of the image doesn't work very well, and both are keyed to that
flag as well.
Change-Id: Id0195bd3b4e454f382782106d6512469106daac5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/10924
Tested-by: build bot (Jenkins)
This option is no longer needed, as FMAP support has been
fully integrated in coreboot
Change-Id: I6121b31bf946532717ba15e12f5c63d2baa95ab2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This will allow more payloads to use the standard linker script
instead of implementing their own.
Change-Id: Ie60120769829f427ceb722109d85859b61dbde31
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
_LDFLAGS+="foo" did not work in my shell (bash on Ubuntu 15.10),
so change it to _LDFLAGS="$_LDFLAGS foo". I'm mildly surprised
that this ever worked.
Change-Id: I59c10f34992240c6df2ec7f24aebc6daafb76493
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14076
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of 500, print 0x00000500 in the ram dump module.
Change-Id: Id250bd99f36dad4088ab88953fb371c400b4231b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14072
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MEMMAP_RAM_ONLY is not an architecture specific option,
hence move it out of the architecture specific menu.
Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is adding complexity to the code more than it saves
space, plus some of the tables could potentially be interesting
outside of the ChromeOS context.
Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Bring defconfig and defconfig-tinycurses in sync, so that
defconfig and defconfig-tinycurses only differ in the selection
of the curses implementation.
Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14069
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The Kconfig lint tool is complaining because this symbol doesn't
exist. Create a temporary definition that can be removed when
the chipset is added.
Change-Id: I6a8abffcc91773aae16721ee1f48c4c64bd6b486
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14091
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change the comparison of build_timeless from -eq to =
This was generating an error if BUILD_TIMELESS wasn't set:
util/genbuild_h/genbuild_h.sh: line 27: [: : integer expression expected
This wasn't causing the script to fail, and won't even if 'set -e' is
added to the script because the error happens inside an 'if' clause,
which is specifically excluded from failue on 'set -e'.
Change-Id: I6a4e147ece23e83ee682d72db35be9e5d4088c78
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14080
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Commit c49014e (timestamp: add tick frequency to exported table)
refactors the code, but forgets to correctly scale the frequency to
megahertz, where the value is read from sysfs, so that printing time
stamp information shows milliseconds instead of microseconds, as can be
seen on the output `cbmem -t` for the ASRock E350M1 below.
```
0:1st timestamp 515
10:start of ramstage 515 (0)
30:device enumeration 515 (0)
40:device configuration 610 (94)
50:device enable 614 (4)
60:device initialization 624 (9)
70:device setup done 639 (14)
75:cbmem post 844 (205)
80:write tables 844 (0)
90:load payload 849 (4)
15:starting LZMA decompress (ignore for x86) 849 (0)
16:finished LZMA decompress (ignore for x86) 869 (20)
99:selfboot jump 869 (0)
Total Time: 350
```
So scale the return value correctly to megahertz, by dividing it with
1000.
```
0:1st timestamp 515,655
10:start of ramstage 515,655 (0)
30:device enumeration 515,663 (7)
40:device configuration 610,620 (94,957)
50:device enable 614,680 (4,059)
60:device initialization 624,618 (9,938)
70:device setup done 639,553 (14,934)
75:cbmem post 844,707 (205,154)
80:write tables 844,710 (2)
90:load payload 849,532 (4,821)
15:starting LZMA decompress (ignore for x86) 849,655 (123)
16:finished LZMA decompress (ignore for x86) 869,903 (20,247)
99:selfboot jump 869,922 (19)
Total Time: 354,261
```
Change-Id: Iea032c62487c7946b6194a90268755034c6350df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/14086
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Initial vendor codes to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.
Change-Id: I9262c9d70a58f0c7427f0658948adf080f2f6d8f
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14030
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This change fixes LPSS ACPI mode. Previously, enabling ACPI mode would
result in unusable devices, as the resources were set to 0 and the devices
were disabled.
lpss.c was copied from intel/baytrail with a few minor adjustment for the
different config structure.
ACPI mode requires setting PcdLpssSioEnablePciMode==LPSS_PCI_MODE_DISABLE
and applying the patch that disables clearing gnvs.
https://review.coreboot.org/#/c/14040/
This doesn't handle the case where the FSP has PcdLpssSioEnablePciMode
set to disable and the devicetree set to default.
Change-Id: I12fffea3820ed948defe7a4f11af6b6363402560
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
If the VBT was provided to the FSP GOP driver then graphics init
will be done as part of SiliconInit step and we can mark that
when it is completed.
This will result in the "oprom" flag being set properly in the
coreboot gpio table and the netboot firmware will have video.
[pg: avoided conflict with Quark that comes without
silicon_init_params.GraphicsConfigPtr]
BUG=chrome-os-partner:50864
BRANCH=glados
TEST=boot image.net.bin on chell and get working graphics
without being setuck in a reboot loop thinking graphics needs
to be started when it already has been.
Change-Id: I0e481b4be57096ed5c60d78e3fa00f3bb2a4eae1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 089d93c712431d1b5923e844137c558994555e95
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331301
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-(cherry picked from commit eeb9d470d8118422feb39ca71106972f2882e240)
Original-Change-Id: Ic59bad27eb9f184ca3eba24643851bfadfe23ab5
Original-Reviewed-on: https://chromium-review.googlesource.com/331355
Reviewed-on: https://review.coreboot.org/13986
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a
did not take into account the default UI setting introduced in
change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM
instability and occassional failure to boot.
Use the correct 1UI value for the modified function semantics.
Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14073
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Since libpayload's LAR support was dropped in If6e36569cd, this module
doesn't compile anymore.
Change-Id: I98f25613a1728e94704d9e9ccb65fd6ba33968b9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14037
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Adds -D / --density option to change the chip density. This is only
implemented for IFD version 1 as I do not have an IFD version 2 to
test this. Density of both chips is changed by default, but a chip
can be selected using -C / --chip.
Change-Id: Iba7affbf6cbefa3147b7b0e019298d905e694716
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/14032
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This change properly assigns resources to the LPE (Low Power Engine for
Audio) and enables ACPI mode.
lpe.c was copied from intel/baytrail with a few minor adjustment for the
different config structure.
ACPI mode requires setting LpeAcpiModeEnable=LPE_ACPI_MODE_ENABLED and
applying the patch that disables clearing gnvs.
https://review.coreboot.org/#/c/14040/
Change-Id: I3fff9aa158bde88e571082642d4f985a5ae1976e
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
That wipes out all previously stored settings and breaks running devices
in ACPI mode.
This more closely matches what is done in intel/baytrail.
Change-Id: Ie993c9f9e1eceb73d016d2df72770a27abb26ec1
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14040
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We want to start testing builds with additional Kconfig options to try
to get more coverage. This will allow us to enable various options to
test without having to add each individual option to the abuild script.
Change-Id: I9bb2bb6f38589e3bcc1282dc4cad51cf6f5149aa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i3100 boards in the chipset.
Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13786
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i810 boards in the chipset.
Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i830 boards in the chipset.
Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
read_dqs_read_data_timing_registers() and
read_read_dqs_timing_control_registers() served essentially
the same function but had slightly different semantics,
causing confusion and needlessly complex Family15h code.
Consolidate both into read_dqs_read_data_timing_registers()
and adjust surrounding code to match new semantics.
Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13994
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add an option to specify a git revision from which to build SeaBIOS.
Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13937
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
Skip logging a wake source when just resetting without coming from
S3 or S5 state. This will prevent the occasional spurious event
like PCI PME from showing up in the event log.
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=run warm reboot teset on chell and ensure no wake source is logged
Change-Id: If739034dc9022b37c90b9cc849a00c604383e70f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7b5cc91adc3ed10df7cebd758cf8144216b9890
Original-Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329846
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331173
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13991
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable SDHCI runtime PM since the display flicker due to
SCC Power Gatingis addressed by 0x82 microcode
BRANCH=glados
BUG=chrome-os-partner:44663
TEST=Check if display flicker is gone when SCC is power-gated
Change-Id: I7d1ac6e77a0d2e0a25414df6130862efcdae2c82
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b552120cfeff09d16cb79652b7de7296121858ba
Original-Change-Id: Id82df475b262e8a91f0a93f8ddf80002b05c52f3
Original-Signed-off-by: Medha Garima <medha.garima@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329651
Original-Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Original-Tested-by: Jenny Tc <jenny.tc@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331172
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13990
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
In order to save more power by shutting down clocks add the
ability to optionally clock gate the 8254 programmable interrupt
timer. When doing this the platforms lose their "PC"-ness which
certain payloads and OSes rely on such as SeaBIOS.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Enabled option on chell. Noted the bit is set upon booting.
Change-Id: I01f9d177bbde417d1efec2e16656a07dcebccbde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 662575aa6a63656dedfa0ce1f202f5fac0205477
Original-Change-Id: Ib4a613cf1c28fc96c36fa2987c4b58a05beab178
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329411
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331171
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode
has been updated since v76, and it requires an an extra VR mailbox
command should be sent from coreboot to pcode.
BUG=chrome-os-partner:48511
BRANCH=None
TEST=Verified on glados, clean S0ix entry and exit.
IMVP8 power is also pretty low
CQ-DEPEND=CL:329393
Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2
Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329480
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13983
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Adding an option to enable VR specific mailbox command.
When set, an extra VR mailbox command specifically for
the MPS IMPV8 VR will be sent.
BUG=chrome-os-partner:48511
BRANCH=None
TEST=Verified on glados, clean S0ix entry and exit.
IMVP8 power is also pretty low
Change-Id: Ia5a23cbb1eca8b463eb7c7c279b74635f1d6b9f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c90a799b51fe35bf184dca6ffce59c89a60f9917
Original-Change-Id: Iffd3fbcb9a15611eefc942529e6cdafba859fb2e
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329393
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13982
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The previous copy of FspUpdVpd.h was not up to date w.r.t. the
FSP release being used for skylake boards. Fix that.
BUG=chrome-os-partner:50863
BRANCH=None
TEST=Built and booted on chell.
Change-Id: I39896c04d35189b0fb2c903eefda4e5b7c57084a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd647f354b8d9946b2217751cf1af845f29191b7
Original-Change-Id: I4ad131af6c563c9c33eb2b9207b13617ff24385d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331290
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13984
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
NOR flash has a hardware limitation that it can't access SRAM region
after 4GB mode is enabled. We add a DRAM DMA region after 0x40000000
for NOR flash driver. So that the NOR flash driver can use this region
after 4GB mode is enabled.
BRANCH=none
BUG=chormoe-os-partner:49229
TEST=Boot to kernel on rev4 w/ 2GB ram and rev3 w/ 4GB ram.
And check /proc/meminfo.
Change-Id: I4a86f0028b26509589ec8d09e2d077920446ece1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dc61ec55187959101a9e891fe5e93928e9b8176e
Original-Change-Id: Ifedc9e2dfba5d294297b3a28134997ac1dd38f94
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327962
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331177
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13989
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect
the DRAM size at runtime.
BUG=chrome-os-partner:49427
BRANCH=none
TEST=Boot to kernel
Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223
Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327961
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331176
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The DRAM size can not be determined before DRAM is initialized. Since
mt8173 only support 2GB and 4GB DRAM models. We map 0x0 to the end of
2GB DRAM address before DRAM is initialized.
BRANCH=none
BUG=none
TEST=boot to kernel
Change-Id: I27a00106b0aa91c3dacfcd2bcd9208f08b108dc5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9720e67c86f0d37a08f7c32e900996c75d60288a
Original-Change-Id: I87d9c6ac11486decde102b7821f550c2f1a51f1c
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327960
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331175
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13987
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Aaron Durbin