Commit Graph

16941 Commits

Author SHA1 Message Date
Philipp Deppenwiese 4cd9a11477 MAINTAINERS: Add maintainer for the intelmetool
If you want to be a maintainer Damien just add yourself to the list.

Change-Id: I15c646fc23d0804a8172da66d9297ab7977e6e6a
Reviewed-on: https://review.coreboot.org/14157
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-26 22:38:46 +01:00
Martin Roth 4c3b156a26 Makefile: Update jenkins-build-toolchain to run build tests
Add coreboot build tests after running the toolchain build.  This
verifies that everything still builds with the new toolchain.

Change-Id: Ifa51db897925c0b77791c83bbcbfd75045c907b5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14156
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-03-26 22:35:01 +01:00
Martin Roth cc9963e3f2 google/intel mainboards: Add missing board_info.txt files
The lint script didn't catch that these mainboard directories didn't
have board_info files.

Add all missing board_info.txt files

Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14117
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-03-25 20:52:04 +01:00
Philipp Deppenwiese d8fe4431ec util/intelmetool: Add intelmetool from Damien Zammit
The intelmetool shows information about the Intel
Management Engine for different platforms.

Original source code can be found under following link:
https://github.com/zamaudio/intelmetool.git

Change-Id: I0eb17833a21eb04cf9245a7312289a4102bec1a9
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/14136
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-25 18:28:03 +01:00
Ben Gardner 77e351d9d1 intel/fsp_baytrail: Fix I2C abort logic
A call to i2c_read() for a non-existent address followed by an i2c_read()
to a valid address results in a false abort status for the 2nd call.

i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT)
i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000000 (I2C_ERR_ABORT)

Because the abort status register is cleared on read and wait_tx_fifo()
reads it twice, the returned status does not contain the abort status.
Fixing that changed the 2nd read to reflect the abort status.

i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT)
i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000001 (I2C_ERR_ABORT)

Bit 0 indicates that the address was not acknowledged by any slave.
That's the abort status from the previous transaction.
So I added a read of the abort status before starting a transaction in
both i2c_read() and i2c_write().

i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT)
i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0 (I2C_SUCCESS)

Tested on a Bay Trail E3845 SoC.

Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14160
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-03-25 18:24:49 +01:00
Ben Gardner 5aecd0e533 intel/fsp_baytrail: Use read32() and write32() in i2c.c
i2c.c uses "*(volatile unsigned int *)" constructs where it could use
read32() and write32().
Switch to using read32() and write32().

The remaining instances in wait_tx_fifo() and wait_rx_fifo() are fixed
in https://review.coreboot.org/#/c/14160/
Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe
(intel/fsp_baytrail: Fix I2C abort logic)

I also fixed a few minor white space issues.

Change-Id: I587551272ac171ef1f42c7eb26daf877dc56646b
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14162
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-03-25 18:24:33 +01:00
Martin Roth 6959f5c915 libpayload: update junit.xml target, clean up output
- Copy each config in configs/ to the junit_config, update each,
in turn, and clean up when done.  This avoids updating the saved
config files and creating dirty files in git.
- Use 'make olddefconfig' instead of 'yes "" | make oldconfig'
- Update clean target to remove junit_config file
- Update distclean target to remove junit.xml

Change-Id: Ib023eb3197f2d8806c73c9c18464157ce3de958f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14164
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-25 18:18:27 +01:00
Martin Roth 591790fca5 buildgcc: Add check for missing libraries and test for zlib
- Add check_for_library routine to test for missing libraries.
- Add a check for zlib.
- Remove 'utility' text from please_install() routine since we can test
for libraries or utilities now.
- Remove incorrect 'solution' text from alternate install since I was
updating that line.

Change-Id: Id5ef28f8bde114cbf4e5a91fc119d42593ea6ab2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14147
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-25 18:15:04 +01:00
Martin Roth 95f7b22dc4 buildgcc: support pigz and lbzip2 decpmpressors if installed.
These are multi-threaded decompressors for .gz and .bz2 compressed
files.  If they're installed, use them to decompress, if they're not,
use the standard single-threaded decompressors.

Change-Id: I397740817e6b234a43b62075899964bdab14f121
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14146
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-25 18:14:31 +01:00
Martin Roth 588c79ddde buildgcc: Fix help text formatting
Add a newline after the supported version text.
Move $TARGETDIR left so that longer paths print better.

Change-Id: If520e1b8657a526dee27763aee62cb78777d020d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14145
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-25 18:11:43 +01:00
Timothy Pearson 54accfe0d6 nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
During maximum read latency training on Family 15h processors,
the maximum read latency was incorrectly set from the NBP1
value instead of the correct NBP0 value.

Modify maximimum read latency training to explicitly operate
on the NBP0 value, and store the previously calculated NBP1
value for reference by other portions of the training algorithm.

Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14150
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-03-24 22:24:11 +01:00
Patrick Georgi 1fc02d1d34 crossgcc: Enable multiple targets for a platform
This is required on powerpc64 to build both little endian and big endian
libgcc.

Change-Id: I295c8ee5e8131d4108e98d1bfd53abb8bd8982b2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14163
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-24 21:49:20 +01:00
Martin Roth 64b35f341b buildgcc: Update coreboot's IASL version to 20160318
Update IASL from 20150619 to 20160318
See release notes at acpica.org

Change-Id: Ic7e7b3956378ad611069e984d5a59c78e4cb08b1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/12817
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-24 21:22:27 +01:00
Julius Werner 6911219ccc edid: Add helper function to calculate bits-per-pixel dependent values
Coreboot and most payloads support three basic pixel widths for the
framebuffer. It assumes 32 by default, but several chipsets need to
override that value with whatever else they're supporting. Our struct
edid contains multiple convenience values that are directly derived from
this (and other properties), so changing the bits per pixel always
requires recalculating all those dependents in the chipset code. This
patch provides a small convenience wrapper that can be used to
consistently update the whole struct edid with a new pixel width
instead, so we no longer need to duplicate those calculations
everywhere.

BUG=None
TEST=Booted Oak in all three pixel widths (which it conveniently all
supports), confirmed that images looked good.

Change-Id: I5376dd4e28cf107ac2fba1dc418f5e1c5a2e2de6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14158
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-24 20:25:12 +01:00
Martin Roth a45a0b70a5 crossgcc: Switch POWER8 to big endian mode
Change-Id: If8c07fb3bee4bf0b531e52fae29890af99f924b4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14161
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-24 18:32:23 +01:00
Timothy Pearson f1d807c5c6 nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()
Change-Id: Ic3f636983cf6ba2796ee56e2a25b56513a4343c1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14148
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-23 22:14:00 +01:00
Paul Kocialkowski 263522db97 armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
As a follow up to Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede,
use as builtin compiler hint instead of inline assembly to allow the
compiler to generate more efficient code.

Change-Id: I690514ac6d8988a6494ad3a77690709d932802b0
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12083
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-23 21:12:31 +01:00
Aaron Durbin eebe0e0db1 soc/intel/apollolake: utilize postcar phase/stage
The current Apollolake flow has its code executing out of
cache-as-ram for the pre-DRAM stages. This is different from
past platforms where they were just executing-in-place against
the memory-mapped SPI flash boot media. The implication is
that when cache-as-ram needs to be torn down one needs to be
executing out of DRAM since the act of cache-as-ram going
away means the code disappears out from under the processor.
Therefore load and use the postcar infrastructure to bootstrap
this process for tearing down cache-as-ram and subsequently
loading ramstage.

Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14141
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-23 14:24:44 +01:00
Aaron Durbin 7f8afe0631 arch/x86: introduce postcar stage/phase
Certain chipsets don't have a memory-mapped boot media
so their code execution for stages prior to DRAM initialization
is backed by SRAM or cache-as-ram. The postcar stage/phase
handles the cache-as-ram situation where in order to tear down
cache-as-ram one needs to be executing out of a backing
store that isn't transient. By current definition, cache-as-ram
is volatile and tearing it down leads to its contents disappearing.
Therefore provide a shim layer, postcar, that's loaded into
memory and executed which does 2 things:

1. Tears down cache-as-ram with a chipset helper function.
2. Loads and runs ramstage.

Because those 2 things are executed out of ram there's no issue
of the code's backing store while executing the code that
tears down cache-as-ram. The current implementation makes no
assumption regarding cacheability of the DRAM itself. If the
chipset code wishes to cache DRAM for loading of the postcar
stage/phase then it's also up to the chipset to handle any
coherency issues pertaining to cache-as-ram destruction.

Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14140
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-23 14:24:30 +01:00
Julius Werner 2b23948535 gpio: Add support for binary_first base3 number system
This patch adds support for an alternative ternary number system in
which group of GPIOs can be interpreted. In this system, the digit
combinations that would form a binary number (i.e. that contain no 'Z'
state) are used to represent the lower values in the way they're used in
the normal binary system, and all the combinations that do contain a 'Z'
are used to represent values above those. We can use this for boards
that originally get strapped with binary board IDs but eventually
require more revisions than that representation allows. We can switch
their code to binary_first base3 and all old revisions with already
produced boards will still get read as the correct numbers.

Credit for the algorithm idea goes to Haran Talmon.

BRANCH=None
BUG=None
TEST=Stubbed out the actual GPIO reading and simulated all combinations
of 4 ternary digits for both number systems.

Change-Id: Ib5127656455f97f890ce2999ba5ac5f58a20cf93
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14116
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-22 21:18:30 +01:00
Martin Roth 4a1c69aa34 MAINTAINERS: Add maintainer for Braswell SOC & Reference board
Change-Id: If3b49c3056abe6e1c1a14578d6c62a866bc6834d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14127
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2016-03-22 19:58:35 +01:00
Aaron Durbin 94271b428e lib/rmodule: export parameters in struct rmod_stage_load
In order for a caller to utilize an rmodule's parameters section
after calling rmodule_stage_load() export the rmodule's parameter
pointer in struct rmod_stage_load.

Change-Id: I9cd51652cf8cdb3fae773256989851638aa1a60f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14139
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-22 13:54:52 +01:00
Lance Zhao f51b12735d soc/apollolake: Add skeleton ACPI entry
Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13348
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-21 23:14:09 +01:00
Patrick Rudolph 5c10abeb73 nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS
Set MMCONF_BASE_ADDRESS to 0xf8000000.
It was already done for some boards, but not all.

The sandybridge chipset code assumes 64 pci buses behind MMCONF.
Therefore, only 64MiB of physical address space is required.

Increasing the address allows to use additional 128MiB of MMIO
space and to use the Intel IGD and a PEG at the same time.

Previously it wasn't possible to use both at the same time,
as two 256MiB areas won't fit into MMIO space.

Test system:
 * Gigabyte GA-B75M-D3H
 * Intel Pentium CPU G2130
 * Onboard GPU Intel IvyBridge Desktop
 * PEG GPU AMD RV770

Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-03-21 23:13:13 +01:00
Patrick Georgi ade606df16 mediatek/mt8173: Enable ARM trusted firmware integration
In Chromium OS downstream this was done together with adding the support
for ATF, but unfortunately ATF upstream isn't ready yet. This commit
is a reminder to enable things once ATF caught up.

Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13968
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 23:12:52 +01:00
Jimmy Huang c54113468b mediatek/mt8173: Remove bl31 board parameters passing mechanism
As the DA9212 and MT6311 external buck can be controlled by hardware
since rev-5 board, we don't need to pass any board specific parameter
to ARM TF.

BRANCH=none
BUG=none
TEST=build pass

Change-Id: I43eebe25ab14d3dd84e8bb4286e2bb55c8c3c063
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c4dfe61c69042e464b384e2e0edbc55eda23a74
Original-Change-Id: I541357fee6afb1ff2d771bcb073f7c9a9db52f00
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332344
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14124
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 23:12:36 +01:00
henryc.chen 316ded82f5 google/oak: Move external buck initialization to coreboot
Remove the code which is passing parameters to ARMTF and move external
buck initilizaton from ARMTF to coreboot.

BRANCH=none
BUG=none
TEST=verified on Oak rev4/rev5

Change-Id: I4f4b30acbee9b42a202b326f2fe4517cb4b9d83c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37bec54b4d8a3bce38878e292e4821da3959026a
Original-Change-Id: Ib81709812a064f6daf13c9b4d6525f1858c81393
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332343
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14123
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 23:12:13 +01:00
henryc.chen 0bb292e384 mediatek/mt8173: Add da9212 driver
Add secondary PMIC for external buck control on Oak rev0/1/2/5

BRANCH=none
BUG=none
TEST=verified on Oak rev4/rev5

Change-Id: Ia000b0c7d61e8396856656247f9627e33b21b19b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 241508e7d781fac8ee085ee81962043dd654c52d
Original-Change-Id: I6c75e2462363a5523bf1ebb03af7a36740293624
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332342
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 23:11:47 +01:00
henryc.chen 7c54d2a760 mediatek/mt8173: Add mt6311 driver
Add secondary PMIC for external buck control on Oak rev3/4

BRANCH=none
BUG=none
TEST=verified on Oak rev4/rev5

Change-Id: I24c18a1cf71fc57deacedcbeb6a100b131c28077
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7f7f8ceac795d8193194a6918a73c4b391009025
Original-Change-Id: I312d8281d2c09d8bc43f092edef3e405d51ee7d0
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332341
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14121
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 23:11:03 +01:00
Yidi Lin d33ebd1374 device: Add i2c read/write register field API
i2c_read_field() - read the value from the specific register field
i2c_write_field() - write the value to the specific register field

BRANCH=none
BUG=none
TEST=none

Change-Id: I2098715b4583c1936c93b3ff45ec330910964304
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0817fc76d07491b39c066f1393a6435f0831b50c
Original-Change-Id: I92c187a89d10cfcecf3dfd9291e0bc015459c393
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332712
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14105
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 23:10:55 +01:00
Timothy Pearson f7d4f73053 nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
Under certain conditions (training abort) BlockRxDqsLock could
remain set in violation of the BKDG.  Ensure BlockRxDqsLock is
reset to 0 after a lane training abort.

Change-Id: I1a49a24d02b2b7cacae074794ec274a424a9e66b
Reviewed-on: https://review.coreboot.org/14144
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 20:30:30 +01:00
Lee Leahy a4d8180913 Documentation: x86 MTRR setup, TempRamExit and MTRR loading
Document how to test TempRamExit and verify the MTRR setup and loading.

TEST=None

Change-Id: I57a604fa139edac4b05453547d3caf185db491e0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 20:12:35 +01:00
Lee Leahy b953d05e60 Documentation/Intel: Add more Galileo Gen2 links
Add datasheet links for the components supporting GPIO.  This includes
I2C I/O ports, I2C PWMs, bus buffers and multiplexers.

TEST=None

Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14114
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:35 +01:00
Lee Leahy e9a6d1a813 Documentation: x86 shadow ROM disable
Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.

TEST=None

Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:06 +01:00
Lee Leahy d75ed0bfd9 soc/intel/quark: Disable the ROM shadow
Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Testing successful display of 0x000ffff0 - 0x000fffff does not match
   the end of the SPI flash.

Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14110
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:46:59 +01:00
Lee Leahy 1f1f2c4d38 mainboard/intel/galileo: Enable SPI controllers
Enable the SPI controllers on the Quark SoC.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Load the SPI driver stack
*  Testing is successful when the time is able to be displayed on a
   set of seven-segment displays controlled by a Maxim MAX6950 SPI
   display controller.

Change-Id: Ic9c4575730c5a9a27cf9a38a41e82d8462467f3f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14109
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:44:41 +01:00
Patrick Rudolph 66a98ee967 device/dram/ddr3: fix debug output
Add missing punctuation and align output.
No functionality is changed.

Old logging output:
  Revision: 11
  Type    : b
  Key     : 2
  Banks   : 8
  Capacity: 4 Gb
  Supported voltages: 1.5V
  SDRAM width       : 8
  Bus extension     : 0 bits
  Bus width         : 64
  Optional features : DLL-Off_mode RZQ/7 RZQ/6
  Thermal features  : ASR ext_temp_range
  Thermal sensor    : no
  Standard SDRAM    : yes
  DIMM Rank1 Address bits mirrored!!!
  DIMM Reference card B
  DIMM Manufacturer ID cd04
  DIMM Part number F3-1866C9-8GSR
  XMP Profile 1
  Max DIMMs per channel: 4
  XMP Revision: 1.3
  Requested voltage: 1500 mV

New logging output:
  Revision           : 11
  Type               : b
  Key                : 2
  Banks              : 8
  Capacity           : 4 Gb
  Supported voltages : 1.5V
  SDRAM width        : 8
  Bus extension      : 0 bits
  Bus width          : 64
  Optional features  : DLL-Off_mode RZQ/7 RZQ/6
  Thermal features   : ASR ext_temp_range
  Thermal sensor     : no
  Standard SDRAM     : yes
  Rank1 Address bits : mirrored
  DIMM Reference card: B
  Manufacturer ID    : cd04
  Part number        : F3-1866C9-8GSR
  XMP Profile        : 1
  Max DIMMs/channel  : 4
  XMP Revision       : 1.3
  Requested voltage  : 1500 mV

Change-Id: Iee4d7a7c0e1070706fb60d7316fad49813963b51
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14083
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 18:31:10 +01:00
Aaron Durbin 57dbbbb596 arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstage
When CONFIG_X86_TOP4G_BOOTMEDIA_MAP was introduced verstage
was not updated. Correct this oversight.

Change-Id: I2775c08798906ba0ba55a361407d7d2b52313229
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14142
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
2016-03-21 14:41:21 +01:00
Martin Roth 57fcae1031 MAINTAINERS: Add maintainers for power8 architecture
Change-Id: I0eedda5f31c2809db7871b81ceb3045b782f9df1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14126
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-03-21 14:35:05 +01:00
Martin Roth 057ce5fa55 MAINTAINERS: Add maintainer to lint scripts, board status & payloads
Change-Id: I3efd4116da1ffda2dbc768d1a447141d8ec76f81
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 14:32:24 +01:00
Martin Roth ae269c0276 payloads: Add a target to print payload git urls and directories
Being able to fetch this list will allow the jenkins builder to securely
fetch the external payloads so we can start testing payload builds.

Change-Id: I777229216b2f11f0f427cd5f8cfa003da4171a77
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14132
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 14:32:02 +01:00
Martin Roth e68a4385d4 payloads/Makefile.inc: Clean up Makefile
- Instead of adding each payload to each common target, create a list
and loop through the list for all of the payloads
- '.phony' doesn't work - the target needs to be uppercase '.PHONY'

Change-Id: I4a7712c94d0f127c2fff8cb8fada4b8132a4ab3b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14131
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 04:03:24 +01:00
Martin Roth c8ed34075b payloads/external: Rename Makefile.inc to Makefile
These makefiles are not included by anything, so they shouldn't be
named Makefile.inc.  Also, having them all be named 'Makefile' makes
some other consolidation work I'm doing much easier.

Change-Id: I1234539ba6a0a6f47d2eb0c21de3da3607c6b8de
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14130
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 04:03:16 +01:00
Stefan Reinauer c2b50ace1b coreinfo: Allow numbers in addition to F keys
When using coreinfo on a serial console (at least
with gtkterm, picocom and minicom on Ubuntu 15.10)
you can't send F keys to the payload. Allow 1..9
for F1..F9

Change-Id: Ie3a11fa1de57c7345737a1ccaff177f407cd5e48
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14065
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-18 21:47:46 +01:00
Jacob Laska f3f654ddb9 src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table
The previous implementation assumed the CPU physical address size to
be 40 which is not true of all platforms. Use an existing function to
obtain the correct CPU physical address to report in the DMAR ACPI
table.

Change-Id: Ia79e9dadecc3f5f6a86ce3789b213222bef482b3
Signed-off-by: Jacob Laska <jlaska91@gmail.com>
Reviewed-on: https://review.coreboot.org/14102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-03-18 19:15:25 +01:00
Furquan Shaikh 331ac1b078 mtrr: Define a function for obtaining free var mtrr
Instead of hard-coding var mtrr numbers in code, use this function to
identify the first available variable mtrr. If no such mtrr is
available, the function will return -1.

Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14115
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-18 19:14:52 +01:00
Yidi Lin 39e55209dc google/oak: Enable RAM_CODE_SUPPORT
BRANCH=none
BUG=chrome-os-partner:50820
TEST=check /proc/device-tree/firmware/coreboot/ram-code

Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361
Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332564
Original-Reviewed-by: Milton Chiang <milton.chiang@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14104
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-18 18:57:17 +01:00
henryc.chen aad2903c9c mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTEN
When system enters suspend, SPM will pull SRCVOLTEN low to turn off some
power rails. VSRMCA7 should follow this pin to turn on/off the power.

BRANCH=none
BUG=none
TEST=verified on Oak rev5

Change-Id: I9d81f855a74fe02a59246ce0c6a7f0e162b9fd0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d92fb1029b810028138eb91b064b63a58b82602f
Original-Change-Id: I37ff0694cbd7b17d5a1ae172c463b4e6aae2b99c
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332345
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14103
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-18 18:56:23 +01:00
Patrick Georgi 32154d7b12 build system: Allow overriding the path to the futility binary
Change-Id: I84e68e8407149780769c3e6a1148c175e42d1025
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/14100
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-17 15:38:47 +01:00
Andrey Petrov b4e5c5eb1e cpu/x86: compile earlymtrr.c code for romstage as well
In order to make this work earlymtrr.c needed to be removed
from intel/truxton/romstage.c. It's not a ROMCC board so
there's no reason to be including .c files.

Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14094
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16 18:56:19 +01:00