Fix regression (supposedly) after commit:
23d62dd lib/bootmem: Add more bootmem tags
Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite
memory regions of the running ramstage. This case is handled
gracefully via a bounce-buffer implementation in arch/x86/boot.c.
Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Copy the script `scripts/config` from Linux (commit 427fbe89 (Merge
branch 'next' of
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux)) into the
newly created directory `scripts`. Here is the original commit message
from 2009.
> commit 8e54701ea85b0ab0971637825a628f5aa2b678a4
> Author: Andi Kleen <andi@firstfloor.org>
> Date: Sat Jan 3 03:21:41 2009 +0100
>
> kconfig: add script to manipulate .config files on the command line
>
> I often change single options in .config files. Instead of using
> an editor or one of the frontends it's convenient to do this from
> the command line. It's also useful to do from automated build scripts
> when building different variants from a base config file.
>
> I extracted most of the CONFIG manipulation code from one of my
> build scripts into a new shell script scripts/config
>
> The script is not integrated with the normal Kconfig machinery
> and doesn't do any checking against Kconfig files, but just manipulates
> that text format. This is always done at make time anyways.
>
> I believe this script would be a useful standard addition for scripts/*
>
> Sample usage:
>
> ./scripts/config --disable smp
> Disable SMP in .config file
>
> ./scripts/config --file otherdir/.config --module e1000e
> Enable E1000E as module in otherdir/.config
>
> ./scripts/config --state smp
> y
> Check state of config option CONFIG_SMP
>
> After merging into git please make scripts/config executable
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Change-Id: Ie32a4459398df8694956dd644f38692017a26388
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26243
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also removes a "chapters mode" that we never used.
Change-Id: Ib301e2f4db0b9678081fa987a5dcc7108bb103a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
SoCs from Skylake on have many settings as so called private con-
figuration registers (PCRs). These are organized as 256 ports with
a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's
BAR to access them.
Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19593
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:80501386
BRANCH=none
TEST=timer and uart work fine
Change-Id: I08644892d34925574f791b000b0035d5afad7022
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26722
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most things still need to be filled in, but this will allow us to build
boards which use this SOC.
BUG=b:80501386
BRANCH=none
TEST=timer and uart work fine
Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26659
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As a result of commit:
[711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device
fizz's chip_info for the LAN driver is being overwritten/nulled, as the
LAN device is on function 2 (PCIe port 3), but the driver info was set
for the post-swapped PCIe port (1).
Move the driver chip_info to function 2/port 3, so that it follows the
PCI device function when swapped after FSP-s, and is correctly passed
to the LAN driver.
Test: boot google/fizz (teemo variant), check cbmem console and
verify ethernet MAC address and LED config correctly set.
Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Why would that be a user visible option? Drop the prompt and the
`default n` and select it automatically when needed. I hope I
caught all its users.
TEST=Confirmed that systems with ELOG_GSMI or DEBUG_SMI compile
and link.
Change-Id: I44aeec530cc333f4ed4c8cfe67c7b5c9d8fb0049
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Clean it up and add all flash chip drivers to postcar stage thereby.
There seem to be SPI controllers that don't need the individual
flash chip drivers. For those postcar support was added in b6b1b23
(console/flashconsole: Enable support for postcar). However for
SPI controllers that need the individual drivers (i.e. those with
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y), linking of the postcar
stage was broken.
For all other stages, the set of compilation units stays the same.
Change-Id: Ib8bdb824bfcf2d31ac696e39f797c4355b765756
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26871
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Let the linker take care of it.
Change-Id: I67d2636ceb042f833c1b44888b98135d728940e0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This code is no longer needed. Removing Kahlee options allows some
Kconfig options to be optimized.
BUG=b:77693343
TEST=Build Grunt, verify that nothing's changed.
Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The initial subsystem ID had a device ID but not a vendor ID.
This change adds the Google vendor ID to the subsystem ID.
Change-Id: I14897da115fd6f2ddd492b6c565bd23227197232
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/26987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Making exceptions for some payload to be loaded near
and under 1 MiB boundary sounds like a legacy 16-bit
x86 BIOS thing we generally do not want under lib/.
Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add tablet motion control config to nami devices.
BUG=None
BRANCH=None
TEST=run evtest
make sure tablet switch value is 1 in tablet mode and 0
when not in tablet mode
Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26970
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage.
Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26984
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use of device_t has been abandoned in ramstage.
Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0
if S0ix is enabled for the platform.
BUG=b:79559085
TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0
flag is set in FACP table - FADT.Flags[21] bit.
Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/26940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This change gets rid of rescnt member in struct device since it is
redundant. "res" member can be used to determine if resource list is
present or not.
BUG=b:80081934
TEST=Verified that static.c generated with and without this CL is
exactly the same for all boards built using abuild.
Change-Id: I73a2361686ad1130716a7d29576f2d02b9ed33c1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change re-factors the device structure in parse tree to be able
to support multidev devices just like non-multidev devices.
With this change, every device has a bus under it which is the parent
of all devices that fall on the bus. If there are duplicate entries in
the devicetree, then there will be multiple buses under the device and
each bus will have its own set of children.
The tree starts out with a root device which has a root bus under
it. This is a special device which is created statically and its
parent is its own root bus. When parsing the device tree file, devices
get added under the root bus as children.
Since this change re-organizes the way devicetree is represented, it
gets rid of latestchild and next_sibling pointers from struct
device. Also, the tree traversal to generate static.c is changed to
breadth-first walk instead of using the next_sibling.
BUG=b:80081934
TEST=Verified using abuild that all boards compile successfully.
Change-Id: Ic8c8a73a247e8e992ab6b1b2cc3131e06fa2e5a1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates queue handling routines to be more generic so that
it can be used by more than just chip queue. Additionally, it provides
functions to dequeue element from head and peek head of a queue which
will be used in a follow-up commit.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: Ibd2de85b48c5d4e2790bf974ea3bb1bd387f66ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Careena uses a different keyboard backlight method, so let the EC
handle the different SKUs and backlight methods.
BUG=b:80106042
TEST=None
Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Until these need to be separated out, use a common file for mainboard
and romstage to make upkeep easier.
BUG=b:80106042
TEST=Build Grunt and Careena
Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This fixes the following failure on certain google/peppy configs:
build/postcar/lib/reset.o: In function `__hard_reset':
/home/pgeorgi/coreboot/src/lib/reset.c:24: undefined reference to `do_hard_reset'
Change-Id: I448a8702a30108f1fc82179a766cbdd209336df7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looking at the 100MHz signal, we were violating the timing requirements.
66MHz still isn't great, but it's a good tradeoff between improving
the signal and losing boot speed time.
This slows down the boot time by about 20mS.
BUG=b:109583457
TEST=Boot grunt, look at signal on scope
Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
During compilation sconfig/main.c gives an error regarding number of
arguments passed in fprintf.
BUG=none
BRANCH=none
TEST=check if compilation warning has been fixed
Change-Id: Ia769cc606a1e3f7e1188cd82235442493d37f664
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26972
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change gets rid of unused 3rd parameter chips to the function
walk_device_tree.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: I255ff030562073b16310fc22a0981808bf2c062f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update to current master.
This includes:
- G45 support
- fixes scaling on eDP (needed for working textmode on eDP)
- gfx_test drawing and moving cursors
- Adding support for Tiling on <= Haswell
- Allow changes to the framebuffer configurarion without resetting the
pipe.
Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26823
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configuring EC_PCH_WAKE_L as an SCI enabled GPIO allows the EC to wake
the AP from S3 on keyboard presses.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) press a key on the internal keyboard
=> system resumes from S3
Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26931
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default we use a 1:1 mapping between GEVENT bits and the corresponding
SCI_MAP entry. However, we still must program the SCI_MAP entries
with the GEVENT number.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) move finger on touchpad for ~1 second
=> system resumes from S3
Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26930
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus
variants) changed the GPE mappings to accomodate for WiFi wake
pin. However, this resulted in TPM interrupt pin being removed from
the GPIO to GPE mapping. Since we do not support true interrupts in
coreboot, GPE_STS registers are used to identify if an interrupt has
triggered. Change in GPE mapping resulted in this information to be
lost when talking to TPM thus resulting in "Timeout wait for tpm
irq".
This change fixes the above issue by assigning GPIO block for TPM
interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to
DW3. DW3 was mapped to NW_31_0 which only has debug header pins and
CNVI pins (none of them are used for reading GPE_STS or as wake
sources).
BUG=b:109824918
TEST=Verified that there are no "Timeout wait for tpm irq" messages
when talking to TPM.
Change-Id: I30768177a838a684948f7485d760c8b83c3190f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TPM over SPI/I2C config selection got changed in
https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the
same.
BUG=None
BRANCH=None
TEST=Build for Soraka & make sure that TPM is probed over I2C interface
rather than SPI.
Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26890
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Scan-build refuses to run if the -fconserve-stack flag is added to
cflags. It fails with the cryptic message "could not find clang line".
Change-Id: Ib1b56ef7d217138a1a195fe993d8e8dd965bd855
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since there are two cameras on Nami and only one camera on Sona.
We need to disable rear camera/DMIC on all Sona sku.
BUG=b:109710674
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Sona
Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since there are two cameras on Nami and only one camera on Pantheon.
We need to disable rear camera/DMIC on all Pantheon sku.
BUG=b:109720689
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Pantheon
Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
From here on, changes should directly touch the release notes, but these
are notable, too.
Change-Id: I602d67f8dd38391663094212cdb4609cdad458ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
As we suppress output now before console_init() is done, the log level
read at start of ramstage is always -1.
Change-Id: Ia078d647c47aaa41ca9f2df9cf8506148ef86538
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Kyösti Mälkki