Commit Graph

22473 Commits

Author SHA1 Message Date
Kyösti Mälkki a26377b063 asus/kcma-d8 kgpe/d16: Fix regression for shutdown
Fix regression caused by commit:

  714709f AMD fam10 ACPI: Use common fixed sleepstates.asl

Adding common sleepstates.asl got lost in rebase process.

Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-06 22:16:05 +00:00
Harsha Priya 130b4a29eb mb/google/{poppy,soraka,eve}: Add imon and vmon params for Max98927 codec
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.

BUG=b:36724448
TEST=After boot, the register dump for  Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.

Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06 19:00:52 +00:00
Harsha Priya 1517735714 driver/i2c/max98927: Add imon and vmon params
This change list adds imon and vmon slot numbers as params for
Maxim 98927 driver. These values are looked up in the kernel driver
to confiure IV feedback for audio playback on speakers.

BUG=b:36724448
TEST=After boot, the register dump for  Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.

Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06 19:00:41 +00:00
Kyösti Mälkki eab5c12ee0 util/cbmem: Pretty print STAGEx_META and _CACHE
Also align entries without name with additional indents.

Change-Id: Ia6aa303daa11e6aec249232aadf4e346bad659d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 17:25:23 +00:00
Nick Vaccaro 900ecbf6e1 soc/intel/cannonlake: remove duplicate uart.c from bootblock
There was already a uart.c added to bootblock. Remove the
duplicate addition.

Change-Id: I2d420ff7437d25a596ee9a120964f8d4bc413bc4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06 17:06:04 +00:00
Lijian Zhao 6d7063c2ac soc/intel/cannonlake: Add Vboot/ChromeOS support
Add Vboot and ChromeOS support in SOC Kconfig, include a separated
verstage in Makefiles.inc as well.

Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 16:53:37 +00:00
Rizwan Qureshi 8688536ca2 mb/google/soraka: enable AER for PCIe root port 0
Enable PCIe Advanced Error Reporting for PCIe root port 0.

Change-Id: I76742801e84449d0910ddadf31d39597df3263b9
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 16:40:01 +00:00
Rizwan Qureshi 6ab4ed40d3 soc/intel/skylake: Add config for enabling PCIe AER
Add a config for enabling/disabling Advanced Error Reporting feature
for PCIe root ports.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06 16:39:58 +00:00
Nicola Corna 33f1273f9f tint: Use the current time as random seed
Previously the random seed was fixed, which led to the same sequence of
blocks for each run.

Now that libpayload has time(), no change is needed in the function
rand_init() of tint.

Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-06 11:53:57 +00:00
Patrick Georgi e41b0d09ba util/testing: Don't keep tegra lp0 build results
We don't actually care for them on our testers, just that the files
can be built.

Change-Id: Ib656a085d70e2aeb1601f1943ad8581af3133839
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21420
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06 11:36:27 +00:00
Kyösti Mälkki 3a19a1c38e AGESA vendorcode: Auto include-dirs
AGESA internal headerfiles are allover the place. Luckily, they
have unique names within the Proc/ tree so include every existing
directory in undefined order.

Change-Id: I86f080e514391a3f0f05d379d24d490ce075060e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-06 09:31:38 +00:00
Patrick Georgi 2997a97a3a 3rdparty/vboot: update to latest master
Besides some internal changes that won't have much effect on coreboot,
the newer version also supports building host tools on systems that
self-designate as i686.

Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06 08:24:04 +00:00
Patrick Georgi cdd3a4327b util/testing: Also test-build tegra's lp0 resume code
The regular build doesn't build it, so it fails every now and then due
to changes in its dependencies.

Make sure we notice these early.

Change-Id: I0603b22887487d8871611d91e6f8ab0ec210bff1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06 08:23:41 +00:00
Kyösti Mälkki ced3a0c249 Revert "soc/intel/cannonlake: Add dummy ACPI DSDT table"
This reverts commit 6c0f3c7ee1.

Reason for revert:
Broke master builds, this was submitted out-of-order, some
of the dependencies have not passed review with +2 yet.

Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-09-06 06:51:02 +00:00
Kyösti Mälkki 3fd259c91d postcar: Add cbmem_stage_cache
S3 resume path executing through postcar was unable
to utilise cached ramstage in CBMEM.

Change-Id: Icc8947c701ca32b4f261ebb78dfc1215b7ed2da0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 05:02:44 +00:00
Kyösti Mälkki ef40c0ce91 AGESA: Drop LATE_CBMEM_INIT in new interface
Change-Id: Iffa6cf495b4649f73a1095732509f195ac828248
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06 05:00:48 +00:00
Kyösti Mälkki 7076aa5745 AGESA: Rename assembly from .inc to .S
Change-Id: I5f90df92e0ac27e98edf23784eeec5618d150430
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06 04:59:09 +00:00
Kyösti Mälkki 5fb2d3074f AGESA f14: Fix duplicate call on S3 resume path
Change-Id: Ie316df6e2babd8b3e9e79f45ea9719b52b0c2902
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06 04:58:58 +00:00
Kyösti Mälkki 38aff1ad41 AGESA f15tn f16kb: Fix ACPI S3 resume for FCH
This recovers FCH configuration on S3 resume path.
Appearst to work, but other defects of HAVE_ACPI_RESUME
must be fixed also before S3 support is re-enabled.

Change-Id: I8d07d2e9dc161b67d854fcc8ec1da1f36900f989
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06 04:58:40 +00:00
Nicola Corna 8f39f1f097 mb/sapphire/pureplatinumh61: Disable the SuperIO serial
There is no serial port on this platform.
In addition, put the LPC serial IRQ into quiet mode.

Change-Id: I4b2c93c51e8ddb8b510f0d7f7e3072befeba5d95
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/21226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06 04:47:59 +00:00
Lijian Zhao 6c0f3c7ee1 soc/intel/cannonlake: Add dummy ACPI DSDT table
A dummy DSDT table will be created for cannonlake.

Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 04:45:19 +00:00
Jonathan Neuschäfer 78fc3fc105 arch/x86/Kconfig: Add deprecation warnings for LATE_CBMEM_INIT
The deprecation of late (post-romstage) CBMEM initialization was
announced in this blog post:
https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/

There are two warnings:
* In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that
  aims to explain the problem.
* In src/mainboard/Kconfig (just below the mainboard selection), there's
  a warning which points the user at LATE_CBMEM_INIT, if such a board is
  selected.

Also update the function that needs to be implemented, as pointed out by
Keith Hui and Kyösti Mälkki.

Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-06 04:43:53 +00:00
Arthur Heymans 250272340b nb/intel/i945/raminit.c: Refactor tRD selection
Inspired by gm45 code, which sets this value the same way.

Some values for tRD on 800 and 1067MHz FSB were set wrong because the
CAS/Freq selection was wrong. CAS was often selected to low and when
fixing CAS this results in tRD being too high, due to an incorrect
lookup table which caused instability.

PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5
on GA-945GCM-S2L.

Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-06 04:41:04 +00:00
Arthur Heymans 3397aa1fd4 device/dram/ddr2: Add a function to normalize tCLK
Also make most significant bit function accessible outside the scope
of this file.

Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-06 04:38:55 +00:00
Naresh G Solanki 5744369025 Makefile: Include Makefile from site-local
Include Makefile from site-local even in absence of DOTCONFIG.
This will allow execution of Makefile option from site-local in absence of
DOTCONFIG as well.

Change-Id: I62d1562687ffe18546add80fdde1196700a65236
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/21303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06 04:37:21 +00:00
Nico Huber 7a1fbdb1e6 Makefile: Keep list of exported variables
This can be useful to unexport them later.

Change-Id: I2ce9eff32d817ec190441550116376843abd1c11
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06 04:36:56 +00:00
Jonathan Neuschäfer 699143aa35 mb/winnet/g170: Drop AMD car.h file from Via mainboard
08f7d1ae0d ("mainboard/via*: Drop AMD car.h file") did the same for all
Via mainboards that were in tree at that time, but the winnet/g170 was
merged a bit later.

Change-Id: Iedb33f4c2fce6fc2cf2669fee4ffb25bf793c92b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06 04:35:37 +00:00
Shawn Chang 027af74999 intelmetool: Add support for Sunrise Point-H
Tested on P10S-M WS.

Change-Id: I62f78fe5ca03bf70497939a12f0036bf247b2aa7
Signed-off-by: Shawn Chang <citypw@gmail.com>
Reviewed-on: https://review.coreboot.org/21301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-09-06 04:35:02 +00:00
Damien Zammit b40c72ae18 abuild: Allow building with any toolchain
Adds -A --any-toolchain option to abuild
This is handy for those who want to test compiling
all board configs with abuild using a non-coreboot toolchain

Change-Id: Idd599b0d2c324ad88ba3c83cdf3b180eb6d1fc80
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06 04:31:30 +00:00
Martin Roth f71a7e66c6 vc/intel/fsp/fsp1_1/braswell: Update FspUpdVpd.h to v 1.1.7.0
Cherry-pick from Chromium 414024e.

Update the FSP 1.1 header to version 1.1.7.0, required for
susequent Chromium cherry-picks and to-be-merged Braswell CrOS devices.

As this header update doesn't shift offsets, only adds new fields
in previously unused/reserved space, it should not negatively impact
existing boards built against the older header version.

Original-Change-Id: Ic378b3c10769c10d8e47c8c76b8e397ddb9ce020
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Tested-by: Martin Roth <martinroth@chromium.org>

Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 04:15:22 +00:00
Jonathan Neuschäfer bdc7567cf5 sb/intel/i82801jx: Use __packed
__packed has been introduced in commit 6a00113de8
("Rename __attribute__((packed)) --> __packed"). Use it.

Change-Id: Ifd33129ae4fbe14c26ceeaaa88832ef994a32dfb
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06 04:14:49 +00:00
Jonathan Neuschäfer f2f27c6bbd soc/amd/stoneyridge: Use __packed
__packed has been introduced in commit 6a00113de8
("Rename __attribute__((packed)) --> __packed"). Use it.

Change-Id: Ie654567ebff884b911de10bd9fef605436e72af8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06 04:14:42 +00:00
Patrick Rudolph 1194aa8d08 ec/lenovo/h8: Add BDC detection support
* Add support for detecting BDC.
* Allows to turn off power to BDC if no card is installed.
* Should fix https://ticket.coreboot.org/issues/99 .

Add the following devicetree values:
* has_bdc_detection
 Set to one to indicate that the following register are sane.
* bdc_gpio_num
 SB GPIO num to read.
* bdc_gpio_lvl
 SB GPIO level for card to be present (usually zero).

Don't enable BDC power if no card is detected.
As there are no devicetree values yet, the new code doesn't
have any effect.

Change-Id: I506de2eca4b820e6d82de6b2c48a5440462e1db5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-06 04:14:25 +00:00
Kyösti Mälkki 746241f114 ACPI S3: Remove conflicting local acpi_get_sleep_type()
We now require EARLY_CBMEM_INIT and romstage_handoff to
support HAVE_ACPI_RESUME. Thus acpi_handoff_wakeup() would
never call an externally defined acpi_get_sleep_type().

Name _sleep_type() was also inapproriate here, as it referred
to hardware-dependent SLP_TYP field of PM1CNT but still
returned ACPI_Sx value instead.

Change-Id: I8dc130f1e86dd7e96922d546f0ae9713188336cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-09-06 04:11:46 +00:00
Subrata Banik b92ad0b077 soc/intel/{cannonlake,skylake}: Fix null pointer dereference in klocwork
This patch fixes klocwork bug due to recent memmap.c
implementation where “Pointer 'dev' returned from call
to function 'dev_find_slot' at line 144 may be NULL.”

Change-Id: I4c74ca410d1a0ba48634ec9928a0d9d1cc20e27a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06 02:34:38 +00:00
Harsha Priya 768843e9e3 intel/skylake: nhlt: Add capture configuration format for IV feedback from max98927
This changelist adds the capture format to be set for max98927. The
nhlt blob is the same but the format params for capture are different
from the render.

BUG=b:36724448
TEST=IV feedback data is of good quality

Change-Id: I135cf4479e89cd2046ff46027f94c0f71aed650e
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05 23:28:36 +00:00
Naresh G Solanki cdc9af9ebd mb/google/soraka: Camera PMIC run time power control
Currently PMIC (tps68470) is in active state even when cameras are not
in use. PMIC is put into SLEEP mode only when entering S3 via
smihandler.

With this change PMIC will be put into SLEEP mode as soon as sensors &
VCM voltage outputs are turned off. This will allow run time power
saving when camera is not in use.

PMIC will be reset in first boot & across S3 & S0ix cycles.

Also, remove the smi handler for PMIC power management & handle it as
part of sensor and VCM ACPI PowerResource.

BUG=b:63903239
TEST= Build for Soraka. Check Camera probe, Capture image across
S3 & S0ix cycles.
Also checked the following & found no regression:
1. Typical camera use cases
2. Stability tests related to camera
3. Reliability tests related to camera
4. PnP tests related to camera
5. Latency related tests with camera

Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05 23:28:10 +00:00
Patrick Georgi 251748426f nvidia/tegra*: Use xcompile for compiler prefix unless specified
GCC_PREFIX is uncommon in the coreboot tree. If not provided, take data
from .xcompile to fill in the blanks.

Change-Id: I711a73be9d35d896198664f0ae213218653f275e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-05 20:17:30 +00:00
Patrick Georgi e8741fe954 Move ADDR32() hack to arch/x86
It's arch specific, so no need to pollute non-x86 with it.

Change-Id: I99ec76d591789db186e8a33774565e5a04fc4e47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21392
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-05 17:24:46 +00:00
Mariusz Szafranski faf7a8e859 mainboard/intel/harcuvar: Add support for Intel Harcuvar CRB
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.

Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-05 13:39:58 +00:00
Mariusz Szafranski a404133547 soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC
This change adds support for Intel Atom C3000 SoC
("Denverton" and "Denverton-NS").
Code is partially based on Apollo Lake/Skylake code.

Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-05 13:39:54 +00:00
Subrata Banik 84c4987eae soc/intel/cannonlake: Set IGD stolen memory size to 64MB
This patch overrides default FSP IGD stolen memory size
UPD value.

TEST=Ensures FSP-M UPD “IgdDvmt50PreAlloc” value is 0x2 (64MB)

Change-Id: I63d992e139810ad203137b34c98d1a463f88b92d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-05 12:43:45 +00:00
Nico Huber 5bceca1c53 nb/intel/common: Write MRC cache at exit of BS_DEV_INIT
We set the SPI lockdown in BS_POST_DEVICE (dev_finalize()) on many plat-
forms now. The SPI controller is initialized at start of BS_DEV_INIT
(dev_initialize()).

The SPI lockdown usually shouldn't be a problem but the SPI driver imple-
mentation lacks full support for the locked interface. Also, some options
exist to lock all flash regions read-only until the next reboot.

Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
2017-09-05 08:27:51 +00:00
Evelyn Huang 824c85c9a5 Documentation: Update Lesson2.md
Update Lesson2.md to include information about updating a commit after
it has been pushed to the remote repository.

Change-Id: Iebf86113b13d859d9c9e3db51e22ea44cb1144f6
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-05 03:54:54 +00:00
Hannah Williams 0805a7e66a soc/intel/common/block/gpio: Fix PAD_DW1_MASK
for case CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y

https://ticket.coreboot.org/issues/128

Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I2b0b9c07ebc99f4b4d7e8c5a72483bedd33e2e07
Reviewed-on: https://review.coreboot.org/21282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-05 00:43:23 +00:00
Patrick Rudolph 4c17098faf Kconfig: Move and rename ADD_VBT_DATA_FILE
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to
INTEL_GMA_ADD_VBT_DATA_FILE.
Depend on Intel platforms to avoid confusing users of non-Intel platforms.

The Intel GMA driver will use the vbt.bin, if present, to fill the
ACPI OpRegion.

Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-04 15:34:10 +00:00
Idwer Vollering 1918c81d65 util/board_status: do a spell check
Change-Id: Ie39be471851586076343b8e9454a9140d4664b8d
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/21322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-04 08:27:27 +00:00
Nico Huber 3f43edc351 libpayload/storage: Add Sunrise Point AHCI PCI id
Change-Id: I9645d76d05014722e4ae0c398d82f7f8e34d6f1c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-02 15:33:50 +00:00
Tsai, Gaggery b2a3ac4705 mainboard/google/fizz: Enable support for DPTF
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for fizz.
It also enables the DPTF flag in the device tree for fizz.

BUG=b:64915426
BRANCH=None
TEST=emerge-fizz coreboot and run DPTF observation tool to make sure
     DPTF is up and running.

Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca
Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-02 15:32:03 +00:00
Nico Huber 3f12d9321a buildgcc: Fix up cross GCC building
Add a missing line-break escape and, rather cosmetic, guard execution of
$CXX which we allow but don't force to be set.

Change-Id: Icf6d3b7de4b7999b8214489f28997964c490d1e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21307
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-02 15:30:52 +00:00