Commit Graph

27169 Commits

Author SHA1 Message Date
Jonathan Neuschäfer 74427cc554 mb/google/kahlee/liara: Document why IOMMU is disabled
Commit d80884ea5a ("mb/google/kahlee: Disable IOMMU") disabled the IOMMU
in all kahlee variants, but omitted the explaining comment only in
liara's devicetree.cb. Copy this comment to liara.

Change-Id: I564013a16217445003467e2a0579abd50597b205
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:27:02 +00:00
Jonathan Neuschäfer 1fb7dd076f util/lint/spelling.txt: Protect "acknowledgement" entry
In commit eceba31c7f ("util/lint: Set "acknowledgement" correct"), the
word "acknowledgement" was removed from util/lint/spelling.txt. A more
robust solution is to comment it out, as done for "sepc" in commit
afa5ec8d5f ("util/lint: Update spelling.txt to latest linux  version").

Change-Id: Ia976dedc9b31190d22e7b946f14709d5c4577f71
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:26:15 +00:00
Jonathan Neuschäfer 726adde879 Documentation/lesson2: Add quotes to increase readability
Change-Id: Ibb041965bb9a97d153ace1f697607e524a6f50ac
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:25:56 +00:00
Jonathan Neuschäfer 018a9af4d5 arch/riscv: Don't hardcode CSR numbers anymore
They are hopefully stable enough by now.

TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS,
     with and without this patch, results in the same coreboot.rom.

Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-18 13:25:45 +00:00
Jonathan Neuschäfer 46275faf50 src/mb/google/*/Kconfig: Consistently use $(...) for variables
Using ${...} in some places is slightly confusing.

Fixes: 395cbb4f97 ("mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree")
Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:25:32 +00:00
Jonathan Neuschäfer 05400b7a2f util/util_readme: Don't recommend running this script with "sh"
util/util_readme/util_readme.sh is specifically a bash script and
requires bash-specific features such as "[[". It doesn't work when run
with a "sh" shell that only implements POSIX features, such as dash.
Thus, tell the user to run the script directly, in which case the #!
line is used.

Change-Id: I5706ffe857c5a148e9776571a377ad8647f9a4c2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:25:21 +00:00
Jonathan Neuschäfer 6b867b8aa8 util/bucts: Add a description.md file
Change-Id: I367703ffcd8d10dec0c67b61c9ebbefd497424fd
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:24:56 +00:00
Jonathan Neuschäfer 85a8169b61 soc/amd/stoneyridge: Improve grammar through punctuation
Change-Id: Iebae12f0b0397b5d4ad1fb09b5d9b847bc63c5d1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:24:45 +00:00
Jonathan Neuschäfer 45e6c82e68 Fix typos involving "the the"
Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-18 13:24:28 +00:00
Arthur Heymans 7ccb2821d2 util/board_status.sh: Fix command for fetching the kernel log
94b761c8e (util/board_status: run dmesg with sudo) attempted to
fetch the console as root locally but instead sudo was put in front
of the remote path which runs as root anyways.

Also unless quotation marks are used the cmd function will see 'sudo'
and 'dmesg' as separate aruguments.

Change-Id: Ib9e9e4b443f4e3ad04c5fda2c2ce626255a190f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-18 13:22:11 +00:00
Amanda Huang 3080fe0a0c mb/google/poppy/variants/nami: Add sku_ids for Syndra
Sync'ing the sku_ids list in the master sku sheet.

BUG=b:112876867

Change-Id: I658e8dc67679b5b528ab267861a1151f50e42414
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-18 09:12:09 +00:00
Duncan Laurie 0907aa0fe6 Revert "vendorcode/google/chromeos: Get ACPI pin from GPIO library"
This reverts commit 6217e9beff.

Reason for revert: boards with CROS_GPIO_VIRTUAL selected in
absence of dedicated recovery GPIO pin is die-ing now at
gpio.c file line. 127

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ief20681b2a7ed4d15fd2d637ae034d54a96b2d6f
Reviewed-on: https://review.coreboot.org/c/30278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-17 19:18:22 +00:00
Sumeet Pawnikar 969ed357f8 mb/google/octopus/variants/fleex: Update Charger throttling settings
Update dptf settings for Charger throttling. Also, update Power
Limit1 minimum value setting from 4.5W to 3W.

BUG=b:112448519
BRANCH=octopus
TEST=Built and tested on Fleex system

Change-Id: I8c2a796ff28254ebef28ed5745b344f925d6e649
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-12-17 17:54:45 +00:00
Justin TerAvest a914152fa6 mb/google/octopus: Add custom SAR values for Bobba
Bobba would prefer to use different SAR values per sku-id for regulatory
compliance. This commit uses the newly added interface for custom wifi
SAR CBFS filenames.

CQ-DEPEND=CL:*729429
BUG=b:120958726
BRANCH=octopus
TEST=build

Signed-off-by: Justin TerAvest <teravest@chromium.org>

Change-Id: I354382d651d65d533459f0ca460ca6fd6de547fd
Reviewed-on: https://review.coreboot.org/c/30223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-17 14:26:46 +00:00
Justin TerAvest c650d6c5bb vendorcode/google: support multiple SAR filenames
Using a fixed filename only allows for one SAR configuration to be
checked into CBFS. However, we have devices with shared firmware that
would desire separate SAR configurations. This change allows boards to
define a function to select one of multiple files stored in CBFS to be
used.

BUG=b:120958726
BRANCH=octopus
TEST=build

Signed-off-by: Justin TerAvest <teravest@chromium.org>

Change-Id: Ib852aaaff39f1e9149fa43bf8dc25b2400737ea5
Reviewed-on: https://review.coreboot.org/c/30222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-17 14:26:10 +00:00
Nico Huber c4d55e4397 soc/intel/fsp_broadwell_de: Drop unused files
It seems they are not included anywhere, Jenkins?

Change-Id: I629cdeb337fce381c69bd1ba0520e524ccdd90dd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/26756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-17 14:16:26 +00:00
Ren Kuo a355b16eb0 mb/google/poppy/variants/nami: perform PL2 setting for bard/ekko
According to bard/ekko cpu types, PL2 need to set the values
1. KBL_U PL2 is 25w.
2. KBL_R PL2 is 29w.

BUG=b:120874861
TEST=power on and check the DUT can boot up well

Change-Id: I5f9d672c4244c363a7cfb362653663a065259fc0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-17 06:45:22 +00:00
Uwe Poeche c092222c39 siemens/mc_apl4: Enable RTC RX6110SA on this mainboard
Enaebl the RTC driver to be used on mc_apl4.

Change-Id: Ib8d2a9f6b8cea47cd10db4dfcc59eec1b21c7993
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-12-17 06:19:38 +00:00
Uwe Poeche 18c1923e13 siemens/mc_apl4: Enable LVDS Display on mc_apl4
Enable PTN3460 chip initialization to get LVDS attached LCD working on
mc_apl4.

Change-Id: I3ccf5398f16831db321eba846d6b041daadf31dd
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-12-17 06:19:23 +00:00
Uwe Poeche 7980d85a13 siemens/mc_apl4: Add GPIO configuration
Add GPIO configuration to match the hardware of mc_apl4.

Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30128
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-17 06:17:49 +00:00
Elyes HAOUAS ad8478f643 superio/ite/it8772f: Fix typo
Change-Id: I4fd7bc6a21909a7facd16799c0ef9296ed65a7b2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-16 16:50:38 +00:00
Elyes HAOUAS 31f2b5aaba superio/ite/it8721f/acpi: Remove unneeded white space
Change-Id: Ie605ab8ff13332359aa44fff12acbadd23dcdf74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-16 16:50:19 +00:00
Subrata Banik befa72b208 cpu/x86: Make mp_get_apic_id() function externally available
This function returns APIC id for respective cpu core.

BUG=b:74436746
BRANCH=none
TEST=mp_get_apic_id() can be accessed in other files now.

Change-Id: I5c5eda8325f941ab84d8a3fe0dae64be71c44855
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/25620
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-15 04:20:27 +00:00
Subrata Banik 78c919bdc8 mb/{intel,google}/{icelake_rvp,dragonegg}: make use of cpu_get_cpuid() helper function
This patch replaces cpuid(1) references from icelake mainboard
with x86 cpu common code library functions cpu_get_cpuid().

- cpu_get_cpuid() -> to get processor id (from cpuid.eax)

Change-Id: Ia12d95d911dd6ee60a3a35937264fef668ad9e35
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-12-15 04:20:10 +00:00
Julius Werner 5d7f5bc973 cheza: Add board reset via Chrome EC
This patch implements board reset on the Cheza board. The real board
reset used by the operating system uses the PMIC, but unfortunately the
PMIC needs to be configured right for that to work. The PMIC
configuration currently happens in the Qualcomm blob (QcLib) that is run
from romstage, but vboot needs to be able to reboot during verstage
already. Porting all the PMIC initialization code to run in the
bootblock seems excessive (and at odds with the goal of doing as little
as possible before verification), so we'll just do a little hack and ask
the EC to perform a cold reset instead. For vboot purposes, this should
work just as well.

BUG=b:118501305
TEST=Hacked vboot code to call vboot_reboot(), confirmed that board
reset and came back up as expected.

Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14 21:09:20 +00:00
Duncan Laurie 674c62bbee soc/intel/cannonlake: Fix CNL-H GPIO pin map
The GPIO pin map for CNL-H does not match with the OS expected
pin numbers.  This has been updated to match what is used by the
Linux kernel pinctrl driver and the pad base has been set for
the GPIO groups to match the sparse GPIO map used by the kernel.

I do not have CNL-H hardware to test this so it is verified against
the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c

Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30134
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14 18:30:58 +00:00
Duncan Laurie 64c9f1584c soc/intel/cannonlake: Add GPIO group pad base for ACPI
The GPIO drivers in Windows and Linux for the Cannonlake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.

It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/

In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation.  The GPIO groups that
are usable by the  OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.

BUG=b:120686247
TEST=tested with write protect GPIO on sarien board.  Before this
change the ACPI pin number was 220 which did not correspond to the
pin number in Linux.  After this change the ACPI number is 303,
which maps to the correct GPIO in Linux.  Now the GPIO value reported
by the kernel changes when the WP pin is toggled in hardware.

Change-Id: I4f1a9e118d7e48f2445ccbb62a12a22e9a832c51
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-14 18:30:46 +00:00
Duncan Laurie 6217e9beff vendorcode/google/chromeos: Get ACPI pin from GPIO library
If the generic GPIO library is enabled the code that generates the
GPIO table in ACPI should attempt to get the GPIO pin value from
the gpio_acpi_pin() function.

BUG=b:120686247
TEST=Tested on Sarien board to ensure that GPIO pin exported by
Chrome OS for the Write Protect signal is correct.

Change-Id: I267694b576009f79bacac6eda5f32bbf51742d78
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-14 18:30:24 +00:00
Duncan Laurie 28e8ae5385 soc/intel/common: Add support for GPIO group pad base
In some situations the GPIO pad numbers used by the OS are not
contiguous and coreboot must provide a way for ACPI to provide
the expected GPIO number to the OS.

To do this each GPIO group can now have a pad base value, which
will be used as the starting pin number for this group and it
is added to the relative pin number of this GPIO to compute the
ACPI pin number for a particular GPIO.

By default this change has no effect because the existing uses
of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the
GPIO number is used as the ACPI pin number without translation.

BUG=b:120686247
TEST=tested on a sarien(cannonlake) board

Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30131
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14 18:30:15 +00:00
Bora Guvendik 1c88cd6c2b mb/google/octopus: Override emmc DLL values for Bobba
New emmc DLL values for Bobba.

BUG=b:120561055
TEST=Boot to OS, chromeos-install, mmc_test

Change-Id: I5a0d9587a91b3c71c042cd8ea360c816ea29fb91
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14 15:46:54 +00:00
Lucas Chen d613da80ce google/grunt: Correct mismatch character hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Part Number
Correct Ram_ID=0b0000 SPD Module Part Number mismatch last alphabet 'C'
to "H5AN8G6NAFR-UHC".

BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all

Change-Id: I4f4b83589ad6b53c0a24f2637f0fe8b92a1168e3
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-14 00:39:43 +00:00
Lucas Chen 9f49b66f46 google/grunt: Correct mismatch character hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part Number
Correct to add Ram_ID=0b0001 SPD Module Part Number mismatch last alphabet 'C'
to "H5ANAG6NAMR-UHC".

BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all

Change-Id: I4d320b2e10c4865456a9a9ccb400db5dd9256b3e
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30177
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-14 00:39:10 +00:00
Subrata Banik 53b08c347f cpuid: Add helper function for cpuid(1) functions
This patch introduces 3 helper function for cpuid(1) :

1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)

Above 3 helper functions are targeted to replace majority of cpuid(1)
references.

Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-13 04:32:57 +00:00
Shelley Chen e3110b8620 mb/google/hatch: Creating skeleton directories and files
Creating skeleton files and directories in mainboard for the new Hatch
board.  This is to facilitate development for different parties
involved.

BUG=None
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-12-13 00:46:09 +00:00
T Michael Turney 4ba64c99e3 cheza: board-level GPIO support
Change-Id: I64e79904c7ad95091ea29d9f80444c4e3b493471
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/29298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-12 18:39:18 +00:00
Karthikeyan Ramasubramanian 82d6f90c5f mb/google/octopus/ampton: Fix the TRACKPAD_INT_ODL GPIO configuration
Update the TRACKPAD_INT1_1V8_ODL GPIO configuration so that it acts as a
wakeup source

BUG=b:119598593
BRANCH=octopus
TEST=Ensure that the system wakes up on trackpad events. Ensure that the
suspend_stress_test runs successfully for 25 iterations.

Change-Id: I28292682cf9c8037abb87d265e49a60139550db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/30171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-12 14:39:40 +00:00
T Michael Turney 303a4bfd4a cheza: TPM/EC enable Kconfig in mainboard
Change-Id: I15cfbbab15b940641c3952f2cfb4b11c37574816
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/29299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-12 02:20:54 +00:00
Jonathan Neuschäfer d2c02420e2 Makefile.inc: Avoid race condition when using 'make -j<N>'
When building coreboot from scratch with 'make -j4', I sometimes see
this error:

    CREATE     build/mainboard/emulation/qemu-riscv/cbfs-file.wblRgZ.out (from /.../coreboot/.config)
    HOSTCC     cbfstool/cbfstool (link)
make[1]: execvp: build/util/kconfig/conf: Permission denied
make[1]: *** [/.../coreboot/util/kconfig/Makefile:92: savedefconfig] Error 127

It happens, I think, because the rule generated by
cbfs-files-processor-defconfig runs 'make savedefconfig', which builds
build/util/kconfig/conf, and something also builds it, at the same time.
Fix this case, by making this rule depend on $(objutil)/kconfig/conf.

The same fix is also precautiously applied to the rule for
$(KCONFIG_AUTOHEADER) in Makefile.

Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-11 16:19:15 +00:00
Tony Huang 1672b6c22c mb/google/octopus/variants/meep: Add 20ms reset delay for WACOM device
Add reset delay in power resource to prevent bind to fail after unbind.

BUG=b:119795901
BRANCH=master
TEST=emerge-octopus coreboot,
     verified that WACOM touchscreen can re-bind successfully.

Change-Id: Idcf02b1c931ed64951995403ec9ebe6b8f2db31d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30099
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-11 08:59:52 +00:00
Lijian Zhao 331dfaff70 mb/google/sarien: Disable unused SATA ports
Disable SATA port 0 and port 1 as that's not used as SATA on platform.

BUG=N/A
TEST=Build and boot up fine on google arcada board.

Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-11 08:59:13 +00:00
Lijian Zhao 2d92b1a3b1 mb/google/sarien: Disable PCH Gigabit LAN
There's no LAN connection on Arcada board, so disable PCH GBE.

BUG=N/A

Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-11 08:59:02 +00:00
Arthur Heymans 4cdb2b9b75 mb/intel/x200: Add data.vbt
There are 2 vendor BIOS's for the Lenovo X200 with the difference being the
settings in the VBT blob to accommodate different backlight frequencies.
Linux however sticks with the setting set by the firmware.

Tested on Lenovo X200 with CCFL backlight.

Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29904
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-11 08:58:13 +00:00
Frans Hendriks b81dcc6c4d soc/intel/braswell/northcluster.c: Fix typo
Correct typo of 'resource'

BUG=N/A
TEST=N/A

Change-Id: I79dde87007759b7cab92061df37fd3a19d5e3d1f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/30125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-11 08:57:53 +00:00
Huayang Duan 2b5067b2c7 mediatek/mt8183: Add DDR driver of tx rx window perbit cal part
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.

Change-Id: I4434897864993e254e1362416316470083351493
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-12-11 08:57:16 +00:00
Ren Kuo 0655761b67 mb/google/poppy/variants/nami: Modify SPD for hynix memory part
correct memory part name
form hynix_dimm_H5ANAG6NCMR-VKC
to hynix_dimm_H5AN4G6NAFR-UHC

BUG=b:113983573
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2018-12-11 02:07:12 +00:00
Patrick Georgi 781ae4aeb7 Documentation/CoC: make clearer it's also for real world events
It's not just for the mailing lists, tools and IRC channel.

Change-Id: I23883cfd8200496f4281d73b6e75fac0d3448a3c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-10 23:45:42 +00:00
Patrick Georgi 493233c4fd Documentation/CoC: revise the instructions for contact the arb team
It's not very helpful to tell somebody who feels wronged "that their
mail was probably lost" (in just as many words).

State why we don't go for a mailing list or ticket system for grievances
and encourage contact multiple people from the outset.

Change-Id: Idac4bcdf8b596a7325e463036c580b17a8b2f27b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-12-10 23:44:57 +00:00
Patrick Georgi e775a90a30 Documentation: Import Code of Conduct from Wiki
I reordered the contacts by current activity and added a link to the
CC-BY-SA license, otherwise it's the original text.

Change-Id: I6f41611db8d9a2f60b24d95abdf30f4fd47cd6f2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-12-10 23:44:38 +00:00
Patrick Georgi 9373e59bb2 Documentation: Add documentation about the release process
It's originally written by Martin who graciously allowed to me rework it
a bit and push it into coreboot's documentation.

Change-Id: I14938d678e4620abec7ed5f0d35dddaf00edda6d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30082
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-10 23:43:51 +00:00
Aamir Bohra df47e1c3e5 mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters
This implementation configures below parameters:

1. Enable SaGv, isclk.
2. Set Pcie rootport enable, Clock source usage and clkreq.
3. Configure SATA and LPSS controllers parameters.
4. Enable CNVI controller, configure Wifi end device under PCIE RP1.
5. Add TPM device support under GSPI1.

Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-10 12:07:43 +00:00