Commit Graph

27169 Commits

Author SHA1 Message Date
Patrick Rudolph 565bebe0b3 util/cbfstool: Support AMD64 rmodules
Add support for 64bit rmodule, as required for relocatable
ramstage on x86_64.

Change-Id: I7fbb3b4c0f76ce82c090b5f16f67a728b6bf94a5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/29874
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 06:05:52 +00:00
Praveen hodagatta pranesh f7fdc3a5ab soc/intel/skylake: Add Sagv enum value definition
SaGv(system Agent Dynamic Frequency) have 4 settings
Disabled, Fixedlow, Fixedhigh, Enabled.
This patch add all 4 settings in enum definition and
used in devicetree.

BUG=None

Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I8f3b56f4d2bea1836373cc505ef5147144100b95
Reviewed-on: https://review.coreboot.org/c/30305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 05:56:02 +00:00
Praveen hodagatta pranesh a86c198cd5 Documentation/../../kblrvp11: Add RVP11 documentation
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd
Reviewed-on: https://review.coreboot.org/c/29859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
2018-12-19 05:51:18 +00:00
Frans Hendriks 9622024a95 soc/intel/braswell/linclude/soc/device_nvs.h: Fix typo
Use 'BAR 1' for the bar1 structure fields.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I1d1278f549fc8a2f3e743e2e2019d3e5f7005614
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/30277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2018-12-19 05:50:48 +00:00
Martin Roth 3f6891108b mb/google/kahlee: Remove board_id check for Liara 2T timings
Use 2T memory timings on Liara for all board IDs.

BUG=b:116082728
TEST=Build & boot on Liara

Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/30285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-12-19 05:49:28 +00:00
Nick Vaccaro 286c6dfd1b mb/google/variant/nocturne: set CONFIG_NO_FADT_8042
Set CONFIG_NO_FADT_8042 to avoid probing for the 8042 controller.
This speeds up boot on nocturne by 1.3 seconds:

  Before change:
  [2.162266] EXT4-fs (mmcblk0p3): mounting ext2 file system using
  	the ext4 subsystem

  After change:
  [0.867735] EXT4-fs (mmcblk0p3): mounting ext2 file system using
  	the ext4 subsystem

BUG=b:120960844
BRANCH=none
TEST=build, flash, and boot nocturne; check dmesg to verify that
boot is faster and that you don't see the following log in dmesg:
	[0.671501] i8042: Probing ports directly.

Change-Id: I62a16e6de5e74fa17970d9967f6d1628497ec1d3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/30283
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 05:49:18 +00:00
Matt DeVillier 5ff460fc2e google/rambi: disable TXE in devicetree for all variants
The TXE PCI device serves no function under Linux, and doesn't
work properly under Windows, so disable/hide it from the OS.

Test: Boot Windows 10 on google/squawks, verify TXE not visible
under Device Manager.

Change-Id: Idaa152e15106b826fd5aa787090acd45719f4228
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19 05:48:25 +00:00
Matt DeVillier a86bbea04d google/cyan: set touchscreen GPIO to non_maskable
Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...]
in additon to changing the touchpad/touchscreen interrupts from
edge to level triggered, also marked them as maskable. This not only
broke the touchpad functionality, but caused issues with the touchpad
as well.  Revert the touchpad to being non_maskable for all cyan
variants with a touchscreen.

Test: boot GalliumOS on google/cyan with a range of kernel versions
(4.15.18, 4.16.13, 4.17.x, 4.18.x) and verify touchscreen functional,
touchpad working properly (not jittery)

Change-Id: I0e0357912f9404af7d0f4e7938a1a94c74810b37
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19 05:48:13 +00:00
Tristan Corrick 58363b4a3b mb/asus/maximus_iv_gene-z: Select NO_UART_ON_SUPERIO
This board doesn't have a UART on the super I/O. Selecting this option
speeds up boot time from ~493 ms to ~416 ms.

Change-Id: I1d84f373831381da79022638e1082adf68f47aad
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-19 05:46:40 +00:00
Jonathan Neuschäfer f3d8580cce arch/riscv: Don't set FPU state to "dirty"
Quoting from the RISC-V Privileged Architecture manual version 1.10,
chapter 3.1.11:

    The FS and XS fields use the same status encoding as shown in Table
    3.3, with the four possible status values being Off, Initial, Clean,
    and Dirty.

    Status   FS Meaning    XS Meaning
        0    Off           All off
        1    Initial       None dirty of clean, some on
        2    Clean         None dirty, some clean
        3    Dirty         Some dirty

Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28987
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 05:46:07 +00:00
Xiang Wang c9add14629 mb/sifive/hifive-unleashed: remove the definition of MAX_CPUS
When I debug with HiFive Unleashed, I found that hart 4 could not be
running. Then find the duplicate MAX_CPUS definition. The correct
MAX_CPUS is located in src/soc/sifive/fu540/Kconfig

Change-Id: I583f6ba548daeeb6c7e341dc3fa8817e7dec5697
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/30179
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 05:44:44 +00:00
Jonathan Neuschäfer ecf25fda86 arch/riscv: Define and use SBI_ENOSYS
Change-Id: Ia7f409ebc7e50383a7e445ef8806953347501dab
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-12-19 05:44:29 +00:00
Arthur Heymans 7d81718cb8 smsc/sch5147: Implement ACPI handling of a few LDN
Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19 05:41:55 +00:00
Arthur Heymans a1e46aea79 mb/lenovo/thinkcentre_a58: Add mainboard
The following was tested:
- Using two DDR2 DIMMs
- S3 sleep and resume (on SeaBIOS it needs sercon disabled)
- Ethernet NIC
- Libgfxinit (native res and textmode)
- SATA
- USB
- 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz)
- PS2 Keyboard
- Serial output

TODO:
- Add ACPI code for SuperIO devices (done in a follow-up patch)
- Add documentation

TESTED with SeaBIOS (sercon disabled), Linux 4.19

Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30239
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 05:40:16 +00:00
Arthur Heymans f1a3503459 superio/smsc: Add SCH5147
There are no public datasheets for this SuperIO. The results are from probing
the registers manually.

Change-Id: Ie5659533c5f224603f918d17942a7057e6701222
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19 05:39:50 +00:00
Arthur Heymans 7ac4096450 mb/foxconn/g41s-k: Don't reprogram inherited subsystemid
Change-Id: I85b5aef758a1ed30c46ed0adabec3293edb0f3fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-19 05:37:19 +00:00
Matt DeVillier 3509138476 soc/intel/skylake: Generate DMAR tables for FSP 1.1 boards
Commit c37b0e3 [soc/intel/skylake: Generate ACPI DMAR table]
only generates DMAR tables for boards using FSP 2.0, which
leaves out Skylake Chromebooks, which use FSP 1.1.

Correct this omission by adding the same functionality for
FSP 1.1 boards.

Test: build/boot on U-series Skylake Chromebook, observe
IOMMU fully functional with intel_iommu=on kernel parameter.

Change-Id: I68837f58aac357fa3f58979fe92d8993fae58640
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-19 05:34:59 +00:00
Lijian Zhao 3ef7449392 soc/intel/cannonlake: Auto turn on HDA controller
Update HDAenable bit in Fsp memory init UPD data base on devicetree
settings.

BUG=N/A
TEST=N/A

Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19 05:32:34 +00:00
Lijian Zhao 6b2c9b1751 mb/google/sarien: Use meaningful SATA mode
Define SATA mode to AHCI mode instead of 0, make devicetree more
readable.

BUG=N/A

Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19 05:30:52 +00:00
Lijian Zhao ba8202948a soc/intel/cannonlake: Declare SATA Mode clear
FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it
more clear in header file.

Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 05:30:23 +00:00
Lijian Zhao fd02ff0375 soc/intel/cannonlake: Enable CPU flexible ratio
CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been
set to zero.

BUG=N/A
TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is
changing.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82
Reviewed-on: https://review.coreboot.org/c/30216
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19 05:29:39 +00:00
Tristan Corrick 8fc49096f9 mb/asrock/h81m-hds: Allow "keep state" for power_on_after_fail
When I added the cmos.layout file, I did not realise that the
southbridge code cleverly emulated the "keep state" option.

Tested on an ASRock H81M-HDS. The `Keep` option works as it should.

Change-Id: I908e59d1e1eedefa6610e7f980afc3c04390a519
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-19 05:26:58 +00:00
Tristan Corrick dcc249e295 sb/intel/lynxpoint: Don't force state keep after power fail
The deleted line crept in with commit 562db3bb3f ("libpayload: find
source of input characters").

Tested on an ASRock H81M-HDS with `power_on_after_fail` set to `Disable`
via CMOS. After this patch, the system no longer powers on as soon as
power is restored after a power failure.

Change-Id: Ie9d9dab9885b285db1c5094c2c8d62aae551f1e7
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-19 05:25:53 +00:00
Frans Hendriks ed7780d353 src/soc/intel/braswell/northcluster.c: Correct Chromeos RAM reservation
RAM is reserved for Chromeos even when Chrome is not used.
Use CONFIG_CHROMEOS to determine if RAM must be reserved.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19 05:25:08 +00:00
Chris Zhou 40a69f3935 mb/google/sarien: Enable ELAN Touchpad and Disable ALPS Touchpad
Enable ELAN Touchpad and Disable ALPS Touchpad

BUG=b:119628524
BRANCH=master
TEST=ELAN Touchpad can work normally.

Change-Id: I7839459a70768fa95ba4871b1915d2ea86419bbb
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-19 05:24:31 +00:00
Lijian Zhao 7182b477eb soc/intel/cannonlake: Amend comment typo
Fix typo of "VGOIO" back to "VGPIO".

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia2b7cb0e5fe2817acc3e3f4656b98dc2462b397f
Reviewed-on: https://review.coreboot.org/c/30147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-19 05:23:58 +00:00
Elyes HAOUAS 21c8f9cab3 mainboard: Remove useless include <device/pci_ids.h>
Change-Id: I4ee3cc42302c44dc80ae1f285579a4d1775aec16
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-19 05:23:18 +00:00
Elyes HAOUAS 19ea62e19d southbridge: Remove useless include <device/pci_ids.h>
Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-19 05:23:03 +00:00
Elyes HAOUAS 17115156b0 {device,drivers}: Remove useless include <device/pci_ids.h>
Change-Id: Ib96bf7d48711f518e36f8d12244b5749d84a0f68
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 05:22:44 +00:00
Elyes HAOUAS 1f4cb326fa northbridge: Remove useless include <device/pci_ids.h>
Change-Id: Ie221a142ed804988a05269d42904aba3ac79e0be
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 05:21:38 +00:00
Elyes HAOUAS af2d6dceab cpu: Remove useless include <device/pci_ids.h>
Change-Id: Ica9514609616e0602fae9b0437d3fa404b645878
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 05:21:09 +00:00
Elyes HAOUAS 6e0044dbf2 soc: Remove useless include <device/pci_ids.h>
Change-Id: Idef8c556ac8c05c5e2047a38629422544392cd62
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 05:20:49 +00:00
Lijian Zhao ae75400ae3 soc/intel/cannonlake: Add Acoustic features
Expose the following FSP UPD interface into coreboot, which is the
following:
AcousticNoiseMitigation
FastPkgCRampDisableIa
FastPkgCRampDisableGt
FastPkgCRampDisableSa
FastPkgCRampDisableFivr
SlowSlewRateForIa
SlowSlewRateForGt
SlowSlewRateForSa
SlowSlewRateForFivr

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I21f53c594a085794474e87eb6781b51db88d0c10
Reviewed-on: https://review.coreboot.org/c/30207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19 05:19:33 +00:00
Jonathan Neuschäfer 4e21dee863 Documentation/*/fit.md: Fix reference to arm64 FIT implementation file
Change-Id: I5844642e25f4c9fe114f621446b4df1075500441
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-19 05:18:58 +00:00
Jonathan Neuschäfer bbaae959bd lib/fit: Normalize spaces in board names to dashes
CONFIG_MAINBOARD_PART_NUMBER sometimes contains spaces, but spaces
inside compat strings aren't nice, so let's convert all spaces to
dashes.

Change-Id: I46f2b2d7091782e04df5476e50698001511f664b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-12-19 05:18:45 +00:00
Jonathan Neuschäfer dca74c16a3 Documentation/soc/intel/icelake: Fix references between documents
Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-19 05:17:58 +00:00
Jonathan Neuschäfer 84eb41d74c Documentation/soc/intel/icelake: Fix indentation in numbered list
Without this patch, the numbers restart at 1 at several points in the
HTML output.

Change-Id: Ie3634775ed9f993b1181785c58d72834183336e1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-19 05:17:39 +00:00
Justin TerAvest afd40b2e2f mb/google/octopus/var/ampton: Tune I2C Audio
The previous settings caused the I2C frequency for the audio bus to be
too high, at 417kHz. The settings in this commit correct the frequency
to 396kHz.

BUG=b:119423345

Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-19 05:14:21 +00:00
Subrata Banik da24535309 soc/intel/icelake: Add GPIO group pad base for ACPI
commit msg copied from
commit id: 64c9f1584c

The GPIO drivers in Windows and Linux for the Icelake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.

It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/

In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation.  The GPIO groups that
are usable by the  OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.

Change-Id: I94fafd8af13cf229f5c467de5179aed021465739
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19 04:53:13 +00:00
Lijian Zhao e5e85e24f7 Revert "google/sarien: Increase BIOS region to 28MB"
This reverts commit ad41f55123.

Reason for revert: <Issue have seen on EVT platform that vboot always fail to verify keyblock A>

BUG=b:121169122

Change-Id: I2790ef3463a228008b614498009fbdc8b493cfb0
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30286
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-18 17:51:05 +00:00
Timothy Pearson 472d68b066 mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during boot
When the BMC firmware module is installed on the KGPE-D16, the
RAM SPD multiplexer lines are disconnected by hardware from the
SP5100 GPIOs and attached to BMC GPIO lines instead.

Set the BMC GPIOs to match the state of the SP5100 GPIOs during
RAM setup.

Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac5
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/19820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18 14:57:41 +00:00
Elyes HAOUAS bb071c1283 southbridge: Remove unneeded include <pc80/mc146818rtc.h>
Change-Id: Ic3f7d4d570cb5e343a9cf616e6e71935f9522b0a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18 13:56:02 +00:00
Elyes HAOUAS 586f24dab4 northbridge: Remove unneeded include <pc80/mc146818rtc.h>
Change-Id: Icae59721db530572d76035975a4e90686bf4fa65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18 13:49:31 +00:00
Elyes HAOUAS 0c0208b590 cpu: Remove unneeded include <pc80/mc146818rtc.h>
Change-Id: I67bc60b9e0eb6289193d698787c18ea4593c991a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18 13:47:33 +00:00
Elyes HAOUAS 2ad59714dd soc: Remove unneeded include <pc80/mc146818rtc.h>
Change-Id: I64e061017ee0b1202ce5482b26c7550e4cd0f0a7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18 13:45:22 +00:00
Elyes HAOUAS fb11c0dcc6 {drivers,superio}: Remove unneeded include <pc80/mc146818rtc.h>
Change-Id: Ia42c1f8559667e7711fac919df8bfbee8455e3cc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18 13:43:16 +00:00
Iru Cai 0766c98aaf nb/intel/haswell: Add server processor host bridge device ID
The device ID is documented in "Intel Xeon Processor E3-1200 v3
Product Family Datasheet volume 2" section 2.2.

Tested with ASRock H81M-HDS with Xeon E3-1271 v3. SeaBIOS payload can
find the boot devices, and GRUB payload can boot Debian GNU/Linux on
the SATA disk.

Change-Id: I999391c9bbc6b39526ad7aec8a6d8fe1a9b5f921
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18 13:33:14 +00:00
Casper Chang 05653ca256 mb/google/sarien/variants/arcada: Enable touchpad and touchscreen
Enable Elan touchpad and WACOM touchscreen

BUG=b:119924134, b:120103010
BRANCH=master
TEST=Verify touchpad and touchscreen on arcada work with this change.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I3dcdb4eeeb32766e64553d9e69e6b7e2b5ba85aa
Reviewed-on: https://review.coreboot.org/c/30146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-18 13:29:55 +00:00
Matt DeVillier a9492a6169 soc/braswell: ensure ACPI opregion restored on S3 with GOP init
The Intel GMA ACPI opregion address needs to be set on S3 resume,
otherwise the Windows display driver fails to re-initialize correctly.
Fix by ensuring the address is set correctly regardless of display
init type used (GOP or VBIOS).

Test: build/boot on google/edgar, ensure internal display functional
following S3 resume under Windows 10.

Change-Id: I471c44e8ba4514e4a2ddf6739109b759145598ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-18 13:28:01 +00:00
Matt DeVillier e5a1a4c5d6 soc/baytrail: add vmx support via CPU_INTEL_COMMON
Mirrors addition to Braswell SoC in commit d3d0f07.

Test: build/boot Windows 10 on Baytrail ChromeOS device, verify Windows shows
virtualization as enabled.

Change-Id: Ia1fafa73325814fed30b2ac91290b682dd8eab04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-18 13:27:43 +00:00